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TL16C552AM Arkusz danych(PDF) 4 Page - Texas Instruments |
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TL16C552AM Arkusz danych(HTML) 4 Page - Texas Instruments |
4 / 38 page TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION NAME FN PN ACK 68 10 I Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place. ACK generates a printer port interrupt during its positive transition. AFD 56 75 I/O Line printer autofeed. AFD is an open-drain line that provides the printer with an active-low signal when continuous form paper is to be autofed to the printer. AFD has an internal pullup resistor to VDD of approximately 10 k Ω. A0, A1, A2 35, 34, 33 51, 50, 49 I Address. The address lines A0 – A2 select the internal registers during CPU bus operations. See Table 2 for the decode of the serial channels and Table 13 for the decode of the parallel printer port. BDO 44 63 O Bus buffer. BDO is the active-high output and is asserted when either the serial channel or the parallel port is read. BDO controls the system bus driver (74LS245 or 54LS245). BUSY 66 8 I Line printer busy. BUSY is an input line from the printer that goes high when the printer is not ready to accept data. CLK 4 14 I Clock. CLK is the external clock input to the baud rate divisor of each ACE. CS0, CS1, CS2 32, 3, 38 48, 13, 54 I Chip select. Each CSx input acts as an enable for the write and read signals for serial channels 1 (CS0) and 2 (CS1). CS2 enables the signals to the printer port. CTS0, CTS1 28, 13 44, 26 I Clear to send. The logical state of each CTSx terminal is reflected in the CTS bit of the modem status register (CTS is bit 4 of the modem status register, written as MSR4) of each ACE. A change of state in either CTS terminal since the previous reading of the associated MSR causes the setting of ∆CTS (MSR0) of each modem status register. DB0 – DB7 14 – 21 27 – 34 I/O Data bits DB0 – DB7. The data bus provides eight I/O lines with 3-state outputs for the transfer of data, control, and status information between the TL16C552A and the CPU. These lines are normally in the high-impedance state except during read operations. DB0 is the least significant bit (LSB) and is the first serial data bit to be received or transmitted. DCD0, DCD1 29, 8 45, 18 I Data carrier detect. DCD is a modem input. Its condition can be tested by the CPU by reading MSR7 (DCD) of the modem status registers. MSR3 ( ∆DCD) of the modem status register indicates whether DCD has changed states since the previous reading of the MSR. DCD has no effect on the receiver. DSR0, DSR1 31, 5 47, 15 I Data set ready. The logical state of the DSRx terminals is reflected in MSR5 of its associated modem status register. ∆DSR (MSR1) indicates whether the associated DSRx terminal has changed states since the previous reading of the MSR. DTR0, DTR1 25, 11 38, 24 O Data terminal ready. Each DTRx can be set low by setting MCR0, modem control register bit 0 of its associated ACE. DTRx is cleared (high) by clearing the DTR bit (MCR0) or whenever a reset occurs. When active (low), DTRx indicates that its ACE is ready to receive data. ENIRQ 43 59 I Parallel port interrupt source mode selection. When ENIRQ is low, the AT mode of interrupts is enabled. In AT mode, INT2 is internally connected to ACK. When ENIRQ is tied high, the PS-2 mode of interrupt is enabled and INT2 is internally tied to the inverse of the PRINT bit in the line printer status register. INT2 is latched high on the rising edge of ACK. INT2 is held until the status register is read, which then clears the PRINT status bit and INT2. ERR 63 5 I Line printer error. ERR is an input line from the printer. The printer reports an error by holding ERR low during the error condition. GND 7, 27, 54 17, 43, 73 Ground (0 V). All terminals must be tied to GND for proper operation. INIT 57 76 I/O Line printer initialize. INIT is an open-drain line that provides the printer with an active-low signal that allows the printer initialization routine to be started. INIT has an internal pullup resistor to VDD of approximately 10 k Ω. INT0, INT1 45, 60 64, 79 O External serial channel interrupt. Each serial channel interrupt 3-state output (enabled by bit 3 of the MCR) goes active (high) when one of the following interrupts has an active (high) condition and is enabled by the interrupt enable register of its associated channel: receiver error flag, received data available, transmitter holding register empty, and modem status. The interrupt is cleared on appropriate service. Upon reset, the interrupt output is in the high-impedance state. |
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