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AD9774ASZ Arkusz danych(PDF) 11 Page - Analog Devices |
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AD9774ASZ Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 24 page AD9774 –11– REV. B PLL CLOCK MULTIPLIER OPERATION The Phase Lock Loop (PLL) Clock Multiplier is intrinsic to the operation of the AD9774 in that it produces the necessary inter- nally synchronized 1 ×, 2× and 4× clocks for the edge triggered latches, interpolation filters and DACs. Figure 24 shows a func- tional block diagram of the PLL Clock Multiplier, which con- sists of a phase detector, a charge pump, a voltage controlled oscillator (VCO), a divide-by-N circuit and some control inputs/ outputs. It produces the required internal clocks for the AD9774 by using one of two possible externally applied reference clock sources applied to either CLKIN or CLK4 ×IN. PLLENABLE and VCO IN/EXT are active HIGH control inputs used to enable the charge pump and VCO respectively. To maintain optimum noise and distortion performance, PLLVDD and DVDD should be set to similar voltage levels. If a separate supply cannot be provided for PLLVDD, PLLVDD can be tied to DVDD using an LC filter network similar to that shown in Figure 41. Many applications will select a reference clock operating at the data input rate as shown in Figure 24. In this case, the external clock source is applied to CLKIN and the PLL Clock Multiplier is fully enabled by tying PLLENABLE and VCO IN/EXT to PLLVDD. Note, CLKIN must adhere to the timing require- ments shown in Figure 1. A 1.5 k Ω resistor and 0.01 µF ceramic capacitor connected in series from LPF to PLLVDD are re- quired to optimize the phase noise vs. settling/acquisition time characteristics of the PLL. PLLLOCK is a control output, ac- tive HIGH, which may be monitored upon system power-up to indicate that the PLL is successfully “locked” to CLKIN. Note, applications employing multiple AD9774 devices will benefit from the PLL Clock Multiplier’s ability to ensure precise simul- taneous updating/phase synchronization of these devices when driven by the same input clock source. PLLDIVIDE is used to preset the “lock-in” range of the PLL. It should be tied to PLLCOM if CLKIN is greater than 10 MHz and to PLLVDD if CLKIN is between 5.5 MHz and 10 MHz. For operation below 5.5 MHz (i.e., input data rates less than 5.5 MSPS), the internal charge pump and VCO should be disabled by tying PLLENABLE and VCO IN/EXT LOW. In this case, the user MUST supply a system clock operating at 4 × the input data rate as discussed below. CONNECT TO PLLCOM CONNECT TO PLLVDD PLL DIVIDE CLK IN/OUT PLLLOCK PLL ENABLE LPF 1.5k 0.01 F +2.7 TO +5.5 VD +2.7 TO +5.5 VD PLL VDD PLL COM VCO VCO IN/EXT DVDD CLK 4 IN DCOM DIVIDE- BY-N 8 4 2 1 VCO CHARGE PUMP PHASE DETECTOR AD9774 Figure 24. Clock Multiplier with PLL Enabled There are two cases in which a user may consider or be required to disable the internal PLL Clock Multiplier and supply the AD9774 with an external 4 × system clock. Applications already containing a system clock operating at four (i.e., 4 ×) the input data rate may consider using it as the master clock source. Ap- plications with input data rates less than 5.5 MSPS must use a master 4 × clock. In any of these cases, the clock source is applied to CLK4 ×IN and the PLL is partially disabled by typing PLLENABLE and VCO IN/EXT to PLLCOM as shown in Figure 25. LPF may remain open since this portion of the PLL circuitry is disabled. The divide-by-N circuit still remains enabled providing a 1 × or 2 × internal clock at CLOCK IN/OUT depending on the state of PLLDIVIDE. Since the digital input data is latched into the AD9774 on the rising edge of the 1 × clock, PLLDIVIDE should be tied to PLLCOM such that the 1 × clock appears as an output at CLOCK IN/OUT. The input data should be stable 5 ns (i.e., data set-up) before the rising edge of the 1 × clock appearing at CLOCK IN/OUT and remain stable for 1 ns after the rising edge (i.e., data hold) to ensure proper latching. Note, the rising edge of the 1 × clock occurs approximately 9 ns to 15 ns relative to the falling edge of the CLK4 × input. If a data timing issue exists between the AD9774 and its external driver device, the CLK4 × input can be inverted via an external gate to ensure proper set-up and hold time. PLL DIVIDE PLLLOCK PLL ENABLE LPF +2.7 TO +5.5 VD PLL VDD PLL COM VCO VCO IN/EXT DVDD CLK 4 IN DCOM DIVIDE- BY-N 8 4 2 1 VCO CHARGE PUMP PHASE DETECTOR AD9774 CLK IN/OUT +2.7 TO +5.5 VD Figure 25. Clock Divider with PLL Disabled DAC OPERATION The 14-bit DAC along with the 1.2 V reference and reference control amplifier is shown in Figure 26. The DAC consists of a large PMOS current source array capable of providing up to 20 mA of full-scale current, IOUTFS. The array is divided into 31 equal currents which make up the five most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose values are 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle-bits current sources. All of these current sources are switched to one or the other of two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. Implement- ing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DAC’s high output impedance (i.e., > 100 k Ω). |
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