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ADSP-21477 Arkusz danych(PDF) 6 Page - Analog Devices |
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ADSP-21477 Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 76 page Rev. C | Page 6 of 76 | July 2013 ADSP-21477/ADSP-21478/ADSP-21479 bits within the 48-bit instruction to create more efficient and compact code. The program sequencer supports fetching these 16-bit and 32-bit instructions from both internal and external SDRAM memory. This support is not extended to the asynchro- nous memory interface (AMI). Source modules need to be built using the VISA option, in order to allow code generation tools to create these more efficient opcodes. On-Chip Memory The processors contain varying amounts of internal RAM and internal ROM which is shown in Table 3 through Table 5. Each block can be configured for different combinations of code and data storage. Each memory block supports single-cycle, inde- pendent accesses by the core processor and I/O processor. The processor’s SRAM can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5M bits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively dou- bles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each mem- ory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. The memory maps in Table 3 through Table 5 display the inter- nal memory address space of the processors. The 48-bit space section describes what this address range looks like to an instruction that retrieves 48-bit memory. The 32-bit section describes what this address range looks like to an instruction that retrieves 32-bit memory. Table 3. ADSP-21477 Internal Memory Space (2M bits) IOP Registers 0x0000 0000–0x0003 FFFF Long Word (64 Bits) Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9 Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF Reserved 0x0004 8000–0x0004 8FFF Reserved 0x0008 AAAA–0x0008 BFFF Reserved 0x0009 0000–0x0009 1FFF Reserved 0x0012 0000–0x0012 FFFF Block 0 SRAM 0x0004 9000–0x0004 BFFF Block 0 SRAM 0x0008 C000–0x0008 FFFF Block 0 SRAM 0x0009 2000–0x0009 7FFF Block 0 SRAM 0x0012 4000–0x0012 FFFF Reserved 0x0004 C000–0x0004 FFFF Reserved 0x0009 000–0x0009 5554 Reserved 0x0009 8000–0x0009 FFFF Reserved 0x0013 0000–0x0013 FFFF Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9 Block 1 ROM (Reserved) 0x000A 0000–0x000AFFFF Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF Reserved 0x0005 8000–0x0005 8FFF Reserved 0x000A AAAA–0x000A BFFF Reserved 0x000B 0000–0x000B 1FFF Reserved 0x0016 0000–0x0016 3FFF Block 1 SRAM 0x0005 9000–0x0005 BFFF Block 1 SRAM 0x000A C000–0x000A FFFF Block 1 SRAM 0x000B 2000–0x000B 7FFF Block 1 SRAM 0x0016 4000–0x0016 FFFF Reserved 0x0005 C000–0x0005 FFFF Reserved 0x000B 0000–0x000B 5554 Reserved 0x000B 8000–0x000B FFFF Reserved 0x0017 0000–0x0017 FFFF Block 2 SRAM 0x0006 0000–0x0006 0FFF Block 2 SRAM 0x000C 0000–0x000C 1554 Block 2 SRAM 0x000C 0000–0x000C 1FFF Block 2 SRAM 0x0018 0000–0x0018 3FFF Reserved 0x0006 1000– 0x0006 FFFF Reserved 0x000C 1555–0x000D 5554 Reserved 0x000C 2000–0x000D FFFF Reserved 0x0018 4000–0x001B FFFF Block 3 SRAM 0x0007 0000–0x0007 0FFF Block 3 SRAM 0x000E 0000–0x000E 1554 Block 3 SRAM 0x000E 0000–0x000E 1FFF Block 3 SRAM 0x001C 0000–0x001C 3FFF Reserved 0x0007 1000–0x0007 FFFF Reserved 0x000E 1555–0x000F 5554 Reserved 0x000E 2000–0x000F FFFF Reserved 0x001C 4000–0x001F FFFF |
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