Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

ADSP-21479BCPZ-1A Arkusz danych(PDF) 4 Page - Analog Devices

Numer części ADSP-21479BCPZ-1A
Szczegółowy opis  SHARC Processor
Download  76 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

ADSP-21479BCPZ-1A Arkusz danych(HTML) 4 Page - Analog Devices

  ADSP-21479BCPZ-1A Datasheet HTML 1Page - Analog Devices ADSP-21479BCPZ-1A Datasheet HTML 2Page - Analog Devices ADSP-21479BCPZ-1A Datasheet HTML 3Page - Analog Devices ADSP-21479BCPZ-1A Datasheet HTML 4Page - Analog Devices ADSP-21479BCPZ-1A Datasheet HTML 5Page - Analog Devices ADSP-21479BCPZ-1A Datasheet HTML 6Page - Analog Devices ADSP-21479BCPZ-1A Datasheet HTML 7Page - Analog Devices ADSP-21479BCPZ-1A Datasheet HTML 8Page - Analog Devices ADSP-21479BCPZ-1A Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 76 page
background image
Rev. C
|
Page 4 of 76
|
July 2013
ADSP-21477/ADSP-21478/ADSP-21479
The block diagram of the ADSP-2147x on Page 1 also shows the
peripheral clock domain (also known as the I/O processor),
which contains the following features:
•IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
• Peripheral and external port buses for core connection
• External port with an asynchronous memory interface
(AMI) and SDRAM controller
•4 units for pulse width modulation (PWM) control
• 1 memory-to-memory (MTM) unit for internal-to-internal
memory transfers
• Digital applications interface that includes four precision
clock generators (PCG), an input data port (IDP/PDAP)
for serial and parallel interconnect, an S/PDIF
receiver/transmitter, four asynchronous sample rate con-
verters, eight serial ports, a shift register, and a flexible
signal routing unit (DAI SRU).
• Digital peripheral interface that includes two timers, a 2-
wire interface, one UART, two serial peripheral interfaces
(SPI), two precision clock generators (PCG), three pulse
width modulation (PWM) units, and a flexible signal rout-
ing unit (DPI SRU).
As shown in the SHARC core block diagram on Page 5, the pro-
cessors use two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. With its SIMD computational hard-
ware, the processors can perform 1.8 GFLOPS running at
300 MHz.
FAMILY CORE ARCHITECTURE
The processors are code compatible at the assembly level with
the ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x,
ADSP-21160, and ADSP-21161, and with the first generation
ADSP-2106x SHARC processors. The ADSP-2147x share archi-
tectural features with the ADSP-2126x, ADSP-2136x, ADSP-
2137x, ADSP-2146x, and ADSP-2116x SIMD SHARC proces-
sors, as shown in Figure 2 and detailed in the following sections.
SIMD Computational Engine
The processors contain two computational processing elements
that operate as a single-instruction, multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. SIMD mode allows
the processor to execute the same instruction in both processing
elements, but each processing element operates on different
data. This architecture is efficient at executing math intensive
DSP algorithms.
SIMD mode also affects the way data is transferred between
memory and the processing elements because twice the data
bandwidth is required to sustain computational operation in the
processing elements. Therefore, entering SIMD mode also dou-
bles the bandwidth between memory and the processing
elements. When using the DAGs to transfer data in SIMD
mode, two data values are transferred with each memory or reg-
ister file access.
SIMD mode is supported from external SDRAM but is not sup-
ported in the AMI.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Timer
The processor contains a core timer that can generate periodic
software interrupts. The core timer can be configured to use
FLAG3 as a timer expired signal.
Data Register File
Each processing element contains a general-purpose data regis-
ter file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register (16 primary, 16 secondary) register files,
combined with the processor’s enhanced Harvard architecture,
allow unconstrained data flow between computation units and
internal memory. The registers in PEX are referred to as
R0–R15 and in PEY as S0–S15.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result registers all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
Universal Registers
Universal registers can be used for general-purpose tasks. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all peripheral control and status
registers.
The data bus exchange register (PX) permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM/DM data bus. These
registers contain hardware to handle the data width difference.
Single-Cycle Fetch of Instruction and Four Operands
The processors feature an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 2). With its separate program and data memory


Podobny numer części - ADSP-21479BCPZ-1A

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Analog Devices
ADSP-21479 AD-ADSP-21479 Datasheet
1Mb / 76P
   SHARC Processor
REV. B
More results

Podobny opis - ADSP-21479BCPZ-1A

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Analog Devices
ADSP-21262 AD-ADSP-21262 Datasheet
1Mb / 44P
   SHARC Processor
REV. A
ADSP-21362 AD-ADSP-21362 Datasheet
2Mb / 52P
   SHARC Processor
REV. A
ADSP-21060CZ-160 AD-ADSP-21060CZ-160 Datasheet
949Kb / 64P
   SHARC Processor
Rev. F
ADSP-21489BSWZ-4B AD-ADSP-21489BSWZ-4B Datasheet
1Mb / 68P
   SHARC Processor
REV. B
ADSP-21060CZ-160 AD-ADSP-21060CZ-160 Datasheet
811Kb / 64P
   SHARC Processor
Rev. F
ADSP-21062LCSZ-160 AD-ADSP-21062LCSZ-160 Datasheet
811Kb / 64P
   SHARC Processor
Rev. F
ADSP-21060KS-160 AD-ADSP-21060KS-160 Datasheet
817Kb / 64P
   SHARC Processor
Rev. F
ADSP-21469BBCZ-3 AD-ADSP-21469BBCZ-3 Datasheet
2Mb / 72P
   SHARC Processor
REV. 0
ADSP-21364 AD-ADSP-21364 Datasheet
853Kb / 52P
   SHARC Processor
Rev. PrB
ADSP-21375 AD-ADSP-21375 Datasheet
1Mb / 42P
   SHARC Processor
Rev. PrB
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com