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AD669 Arkusz danych(PDF) 11 Page - Analog Devices |
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AD669 Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 12 page AD669 REV. A –11– NOISE In high resolution systems, noise is often the limiting factor. A 16-bit DAC with a 10 volt span has an LSB size of 153 µV (–96 dB). Therefore, the noise floor must remain below this level in the frequency range of interest. The AD669’s noise spectral density is shown in Figures 12 and 13. Figure 12 shows the DAC output noise voltage spectral density for a 20 V span excluding the reference. This figure shows the l/f corner frequency at 100 Hz and the wideband noise to be below 120 nV/ √Hz. Figure 13 shows the reference noise voltage spectral density. This figure shows the reference wideband noise to be below 125 nV/ √Hz. 1000 1 11M 100 10 10 100k 10k 1k 100 10M FREQUENCY – Hz Figure 12. DAC Output Noise Voltage Spectral Density 1000 1 1 1M 100 10 10 100k 10k 1k 100 10M FREQUENCY – Hz Figure 13. Reference Noise Voltage Spectral Density BOARD LAYOUT Designing with high resolution data converters requires careful attention to board layout. Trace impedance is the first issue. A 306 µA current through a 0.5 Ω trace will develop a voltage drop of 153 µV, which is 1 LSB at the 16-bit level for a 10 V full-scale span. In addition to ground drops, inductive and ca- pacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital sig- nals. Finally, power supplies need to be decoupled in order to filter out ac noise. Analog and digital signals should not share a common path. Each signal should have an appropriate analog or digital return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recom- mended to provide low impedance signal paths. Separate analog and digital ground planes should also be utilized, with a single interconnection point to minimize ground loops. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. One feature that the AD669 incorporates to help the user layout is the analog pins (VCC, VEE, REF OUT, REF IN, SPAN/BIP OFFSET, VOUT and AGND) are adjacent to help isolate analog signals from digital signals. SUPPLY DECOUPLING The AD669 power supplies should be well filtered, well regu- lated, and free from high frequency noise. Switching power sup- plies are not recommended due to their tendency to generate spikes which can induce noise in the analog system. Decoupling capacitors should be used in very close layout prox- imity between all power supply pins and ground. A 10 µF tanta- lum capacitor in parallel with a 0.1 µF ceramic capacitor provides adequate decoupling. VCC and VEE should be bypassed to analog ground, while VLL should be decoupled to digital ground. An effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. The circuit layout should attempt to locate the AD669, associated analog circuitry and interconnections as far as possible from logic circuitry. A solid analog ground plane around the AD669 will isolate large switching ground currents. For these reasons, the use of wire wrap circuit construction is not recommended; careful printed circuit construction is preferred. GROUNDING The AD669 has two pins, designated analog ground (AGND) and digital ground (DGND.) The analog ground pin is the “high quality” ground reference point for the device. Any exter- nal loads on the output of the AD669 should be returned to analog ground. If an external reference is used, this should also be returned to the analog ground. If a single AD669 is used with separate analog and digital ground planes, connect the analog ground plane to AGND and the digital ground plane to DGND keeping lead lengths as short as possible. Then connect AGND and DGND together at the AD669. If multiple AD669s are used or the AD669 shares ana- log supplies with other components, connect the analog and digital returns together once at the power supplies rather than at each chip. This single interconnection of grounds prevents large ground loops and consequently prevents digital currents from flowing through the analog ground. |
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