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AD7890SQ-10QML Arkusz danych(PDF) 8 Page - List of Unclassifed Manufacturers

Numer części AD7890SQ-10QML
Szczegółowy opis  MICROCIRCUIT, LINEAR, 8-CHANNEL, 12-BIT SERIAL, DATA ACQUISITION SYSTEM, MONOLITHIC SILICON
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STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-95615
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
C
SHEET
8
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - continued.
Test
Symbol
Conditions 1/, 3/, 5/
-55
°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Unit
Min
Max
Data valid to SCLK falling
edge hold time
t11
9, 10, 11
01
10
ns
TFS to SCLK falling edge
hold time
t12
9, 10, 11
01
20
ns
RFS low to SCLK falling
edge setup time
t13
9, 10, 11
01
20
ns
RFS low to data valid delay
8/
t14
9, 10, 11
01
40
ns
SCLK high pulse width
t15
9, 10, 11
01
50
ns
SCLK low pulse width
t16
9, 10, 11
01
50
ns
SCLK rising edge to data
valid delay 8/
t17
9, 10, 11
01
35
ns
RFS to SCLK falling edge
hold time
t18
9, 10, 11
01
20
ns
Bus relinquish time after
rising edge of RFS
t19
9, 10, 11
01
50
ns
Bus relinquish time after
rising edge of SCLK 9/
t19A
9, 10, 11
01
90
ns
TFS low to SCLK falling edge
setup time
t20
9, 10, 11
01
20
ns
Data valid to SCLK falling
edge setup time
t21
9, 10, 11
01
10
ns
Data valid to SCLK falling
edge hold time
t22
9, 10, 11
01
15
ns
TFS low to SCLK falling edge
hold time
t23
9, 10, 11
01
40
ns
1/ VDD = +5.25 V, AGND = DGND = 0 V, REF IN = +2.5 V, fCLKIN = 2.5 MHz external, MUX OUT connected to SHA IN.
2/ Full-scale error match applied to both positive and negative full scale.
3/ Subgroups 9, 10, and 11 are tested initially and after any changes which may affect these parameters. See figures 3 and 4.
4/ Analog inputs must be at 0 V to achieve correct power-down current.
5/ All input signals are specified with tr = tf = 5 ns (10% to 90% 0f 5 V) and timed from a voltage level of 1.6 V. Tested initially
and after any design changes which may affect these parameters.
6/ Production tested with fCLKIN at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.
7/ Specified using 10% and 90% points on waveform of interest.
8/ These numbers are measured with the load circuit of figure 3 and defined as the time required for the output to cross 0.8 V
or 2.4 V.
9/ These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit
of figure 3. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF
capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as
such are independent of external bus loading capacitances.


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