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ADS131E04IPAG Arkusz danych(PDF) 10 Page - Texas Instruments |
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ADS131E04IPAG Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 60 page ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com PIN ASSIGNMENTS (continued) NAME TERMINAL FUNCTION DESCRIPTION GPIO1 42 Digital input/output General-purpose input/output pin GPIO2 44 Digital input/output General-purpose input/output pin GPIO3 45 Digital input/output General-purpose input/output pin GPIO4 46 Digital input/output General-purpose input/output pin IN1N(1) 15 Analog input Differential analog negative input 1 IN1P(1) 16 Analog input Differential analog positive input 1 IN2N(1) 13 Analog input Differential analog negative input 2 IN2P(1) 14 Analog input Differential analog positive input 2 IN3N(1) 11 Analog input Differential analog negative input 3 IN3P(1) 12 Analog input Differential analog positive input 3 IN4N(1) 9 Analog input Differential analog negative input 4 IN4P(1) 10 Analog input Differential analog positive input 4 Differential analog negative input 5 IN5N(1) 7 Analog input (ADS131E06 and ADS131E08 only) IN5P(1) 8 Analog input Differential analog positive input 5 (ADS131E06 and ADS131E08 only) Differential analog negative input 6 IN6N(1) 5 Analog input (ADS131E06 and ADS131E08 only) IN6P(1) 6 Analog input Differential analog positive input 6 (ADS131E06 and ADS131E08 only) IN7N(1) 3 Analog input Differential analog negative input 7 (ADS131E08 only) IN7P(1) 4 Analog input Differential analog positive input 7 (ADS131E08 only) IN8N(1) 1 Analog input Differential analog negative input 8 (ADS131E08 only) IN8P(1) 2 Analog input Differential analog positive input 8 (ADS131E08 only) NC 27, 29, 62, 64 — No connection, leave floating OPAMPN 61 Analog Op amp inverting input OPAMPP 60 — Op amp noninverting input OPAMPOUT 63 Analog Op amp output PWDN 35 Digital input Power-down; active low RESET 36 Digital input System reset; active low RESV1 31 Digital input Reserved for future use; must tie to logic low (DGND) SCLK 40 Digital input SPI clock START 38 Digital input Start conversion TESTN(1) 18 Analog input/output Internal test signal, negative signal TESTP(1) 17 Analog input/output Internal test signal, positive signal VCAP1 28 Analog input/output Analog bypass capacitor VCAP2 30 — Analog bypass capacitor VCAP3 55 — Analog bypass capacitor VCAP4 26 Analog output Analog bypass capacitor VREFN 25 Analog input Negative reference voltage VREFP 24 Analog input/output Positive reference voltage (1) Connect unused terminals to AVDD. 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS131E04 ADS131E06 ADS131E08 |
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