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SN74GTL1655DGGR Arkusz danych(PDF) 1 Page - Texas Instruments |
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SN74GTL1655DGGR Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 17 page www.ti.com FEATURES DESCRIPTION/ORDERING INFORMATION DGG PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1OEAB 1OEBA VCC 1A1 GND 1A2 1A3 GND 1A4 GND 1A5 GND 1A6 1A7 VCC 1A8 2A1 GND 2A2 2A3 GND 2A4 2A5 GND 2A6 GND 2A7 VCC 2A8 GND 2OEAB 2OEBA CLK 1LEAB 1LEBA VERC GND 1B1 1B2 GND 1B3 1B4 1B5 GND 1B6 1B7 VCC 1B8 2B1 GND 2B2 2B3 GND 2B4 2B5 VREF 2B6 GND 2B7 2B8 BIAS VCC 2LEAB 2LEBA OE The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION SCBS696I – JULY 1997 – REVISED APRIL 2005 • Member of the Texas Instruments Widebus™ Family • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference • Translates Between GTL/GTL+ Signal Level and LVTTL Logic Levels • High-Drive (100 mA), Low-Output-Impedance (12 Ω) Bus Transceiver (B Port) • Edge-Rate-Control Input Configures the B-Port Output Rise and Fall Times • Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port • Distributed VCC and GND Pins Minimize High-Speed Switching Noise The SN74GTL1655 is a high-drive (100 mA), low-output-impedance (12 Ω) 16-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. This device is partitioned as two 8-bit transceivers and combines D-type flip-flops and D-type latches to allow for transparent, latched, and clocked modes of data transfer similar to the '16501 function. This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry. The high drive is suitable for driving double-terminated low-impedance backplanes using incident-wave switching. higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels, but are not 5-V tolerant. VREF is the reference input voltage for the B port. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, UBT, OEC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1997–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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