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SN74ALVCH162373GR Arkusz danych(PDF) 1 Page - Texas Instruments |
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SN74ALVCH162373GR Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 15 page www.ti.com FEATURES DESCRIPTION/ORDERING INFORMATION DGG OR DL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE The outputs, which are designed to sink up to 12 mA, include equivalent 26- Ω resistors to reduce overshoot and SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES583A – JULY 2004 – REVISED OCTOBER 2004 • Member of the Texas Instruments Widebus™ Family • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • Output Ports Have Equivalent 26- Ω Series Resistors, So No External Resistors Are Required • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH162373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. undershoot. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74ALVCH162373DL SSOP - DL ALVCH162373 Tape and reel SN74ALVCH162373LR -40 °C to 85°C TSSOP - DGG Tape and reel SN74ALVCH162373GR ALVCH162373 VFBGA - GQL Tape and reel SN74ALVCH162373KR VH2373 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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