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ADP3211AMNR2G Arkusz danych(PDF) 4 Page - ON Semiconductor

Numer części ADP3211AMNR2G
Szczegółowy opis  7-Bit, Programmable, Single-Phase, Synchronous Buck Controller
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Producent  ONSEMI [ON Semiconductor]
Strona internetowa  http://www.onsemi.com
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ADP3211AMNR2G Arkusz danych(HTML) 4 Page - ON Semiconductor

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ADP3211, ADP3211A
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4
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
PWRGD
Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the
VID DAC defined range.
2
IMON
Current Monitor Output. This pin sources current proportional to the output load current. A resistor connected
to FBRTN sets the current monitor gain.
3
CLKEN
Clock Enable Output. Open drain output. The pull−high voltage on this pin cannot be higher than VCC.
4
FBRTN
Feedback Return Input/Output. This pin remotely senses the GMCH voltage. It is also used as the ground
return for the VID DAC and the voltage error amplifier blocks.
5
FB
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
6
COMP
Voltage Error Amplifier Output and Frequency Compensation Point.
7
GPU
GMCH/CPU select pin. Connect to ground when powering the CPU. Connect to 5.0 V when powering the
GMCH. When GPU is connected to ground, the boot voltage is 1.1 V for the ADP3211 and 1.2 V for the
ADP3211A. When GPU is connected to 5.0 V, there is no boot voltage.
8
ILIM
Current Limit Set pin. Connect a resistor between ILIM and CSCOMP to the current limit threshold.
9
IREF
This pin sets the internal bias currents. A 80 kW is connected from IREF to ground.
10
RPM
RPM Mode Timing Control Input. A resistor is connected from RPM to ground sets the RPM mode turn−on
threshold voltage.
11
RT
PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM oscillator
frequency.
12
RAMP
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets
the slope of the internal PWM stabilizing ramp.
13
LLINE
Load Line Programming Input. The center point of a resistor divider connected between CSREF and
CSCOMP tied to this pin sets the load line slope.
14
CSREF
Current Sense Reference Input. This pin must be connected to the opposite side of the output inductor.
15
CSFB
Non−inverting Input of the Current Sense Amplifier. The combination of a resistor from the switch node to this
pin and the feedback network from this pin to the CSCOMP pin sets the gain of the current sense amplifier.
16
CSCOMP
Current Sense Amplifier Output and Frequency Compensation Point.
17
GND
Analog and Digital Signal Ground.
18
PGND
Low−Side Driver Power Ground. This pin should be connected close to the source of the lower MOSFET(s).
19
DRVL
Low−Side Gate Drive Output.
20
PVCC
Power Supply Input/Output of Low−Side Gate Driver.
21
SW
Current Return For High−Side Gate Drive.
22
DRVH
High−Side Gate Drive Output.
23
BST
High−Side Bootstrap Supply. A capacitor from this pin to SW holds the bootstrapped voltage while the
high−side MOSFET is on.
24
VCC
Power Supply Input/Output of the Controller.
25 to 31
VID6 to VID0
Voltage Identification DAC Inputs. A 7−bit word (the VID Code) programs the DAC output voltage, the
reference voltage of the voltage error amplifier without a load (see the VID Code Table, Table NO TAG). In
normal operation mode, the VID DAC output programs the output voltage to a value within the 0 V to 1.5 V
range. The input is actively pulled down.
32
EN
Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, and pulls PWRGD low.


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