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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TDA9330H Arkusz danych(PDF) 10 Page - NXP Semiconductors |
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TDA9330H Arkusz danych(HTML) 10 Page - NXP Semiconductors |
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10 / 56 page  2002 Jun 04 10 Philips Semiconductors Preliminary specification I2C-bus controlled TV display processors TDA933xH series The minimum value for the vertical wait setting is 8 line periods. If the setting is lower than 8, the wait period will remain at 8 line periods. The E-W drive circuit has a single-ended output. The E-W geometry can be adjusted on the following parameters: • Horizontal width with increased range because of the ‘zoom’ feature • E-W parabola/width ratio • E-W upper corner/parabola ratio • E-W lower corner/parabola ratio • E-W trapezium. The IC has an EHT compensation input which controls both the vertical and the E-W output signals. The relative control effect on both outputs can be adjusted via the I2C-bus (sensitivity of vertical correction is fixed; E-W correction variable). To avoid damage to the picture tube in the event of missing or malfunctioning vertical deflection, a vertical guard function is available at the sandcastle pin (pin SCO). The vertical guard pulse from the vertical output stage (TDA835x) should be connected to the sandcastle pin, which acts as a current sense input. If the guard pulse is missing or lasts too long, bit NDF is set in the status register and the RGB outputs are blanked. If the guard function is disabled via bit EVG, only status bit NDF is set. The IC also has inputs for flash and overvoltage protection. More details about these functions are given in Chapter “Characteristics”; note 43. I2C-BUS SPECIFICATION The slave address of the IC is given in Table 1. The circuit operates up to clock frequencies of 400 kHz. Valid subaddresses: 00 to 1F, subaddress FE is reserved for test purposes. The auto-increment mode is available for subaddresses. It should be noted that the status bytes cannot be addressed separately, they can only be read via the auto-increment mode. Table 1 Slave address (8C) A6 A5 A4 A3 A2 A1 A0 R/W 1000110 1/0 |
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