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74LVX125SJ Arkusz danych(PDF) 1 Page - Fairchild Semiconductor |
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74LVX125SJ Arkusz danych(HTML) 1 Page - Fairchild Semiconductor |
1 / 8 page ©1994 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVX125 Rev. 1.4.0 February 2008 74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs Features ■ Input voltage level translation from 5V to 3V ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance General Description The LVX125 contains four independent non-inverting buffers with 3-STATE outputs. The inputs tolerate volt- ages up to 7V allowing the interface of 5V systems to 3V systems. Ordering Information Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Connection Diagram Pin Description Logic Symbol IEEE/IEC Truth Table H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial Order Number Package Number Package Description 74LVX125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description An Inputs OEn Output Enable Inputs On Outputs Inputs Output OEn An On LLL LH H HX Z |
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