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ADL5372ACPZ-R21 Arkusz danych(PDF) 4 Page - Analog Devices |
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ADL5372ACPZ-R21 Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 24 page ADL5372 Rev. 0 | Page 4 of 24 Parameter Conditions Min Typ Max Unit LO INPUTS LO Drive Level1 Characterization performed at typical level −6 0 +6 dBm Input Return Loss See Figure 9 for a plot of return loss vs. frequency −12 dB BASEBAND INPUTS Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN I and Q Input Bias Level 500 mV Input Bias Current Current sourcing from each baseband input with a bias of 500 mV dc2 45 μA Input Offset Current 0.1 μA Differential Input Impedance 2900 kΩ Bandwidth (0.1 dB) LO = 1900 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc 70 MHz Bandwidth (1 dB) LO = 1900 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc 350 MHz POWER SUPPLIES Pin VPS1 and Pin VPS2 Voltage 4.75 5.25 V Supply Current 165 mA 1 High LO drive reduces noise at a 6 MHz carrier offset in GSM applications. 2 See V-to-I Converter section for architecture information. |
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