ADP3330

–8–

REV. A

APPLICATION INFORMATION

Capacitor Selection

Output Capacitors: as with any micropower device, output

transient response is a function of the output capacitance. The

ADP3330 is stable with a wide range of capacitor values, types

and ESR (anyCAP). A capacitor as low as 0.47

µF is all that is

needed for stability; larger capacitors can be used if high output

current surges are anticipated. The ADP3330 is stable with

extremely low ESR capacitors (ESR

≈ 0), such as Multilayer

Ceramic Capacitors (MLCC) or OSCON. Note that the

effective capacitance of some capacitor types may fall below the

minimum at cold temperature. Ensure that the capacitor

provides more than 0.47

µF at minimum temperature.

Input Bypass Capacitor: an input bypass capacitor is not strictly

required but it is advisable in any application involving long

input wires or high source impedance. Connecting a 0.47

µF

capacitor from IN to ground reduces the circuit’s sensitivity to

PC board layout. If a larger value output capacitor is used, then

a larger value input capacitor is also recommended.

Noise Reduction

A noise reduction capacitor (C

the noise by 6 dB–10 dB (Figure 21). Low leakage capacitors in

10 pF–500 pF range provide the best performance. Since the

noise reduction pin (NR) is internally connected to a high imped-

ance node, any connection to this node should be carefully done

to avoid noise pickup from external sources. The pad connected

to this pin should be as small as possible and long PC board

traces are not recommended.

When adding a noise reduction capacitor, use the following

guidelines:

•

Maintain a minimum load current of 1 mA when not in

shutdown.

•

For CNR values greater than 500 pF, add a 100 k

Ω series

resistor (RNR).

It is important to note that as CNR increases, the turn-on time

will be delayed. With CNR values greater than 1 nF, this delay

may be on the order of several milliseconds.

+

–

+

C1

0.47 F

IN

–

ADP3330-3

SD

GND

OUT

330k

C2

0.47 F

R1

CNR

NR

ERR

RNR

Figure 21. Noise Reduction Circuit

Chip-on-Lead Package

The ADP3330 uses a patented Chip-on-Lead package design to

ensure the best thermal performance in an SOT-23 footprint. In

a standard SOT-23, the majority of the heat flows out of the

ground pin. This new package uses an electrically isolated die

attach that allows all pins to contribute to heat conduction.

This technique reduces the thermal resistance to 190

°C/W on a

2-layer board as compared to >230

°C/W for a standard SOT-23

leadframe. Figure 22 shows the difference between the standard

SOT-23 and the Chip-on-Lead leadframes.

SILICON

DIE

a. Normal SOT-23-6 Package

SILICON DIE WITH

ELECTRICALLY

ISOLATED

DIE ATTACH

b. Thermally Enhanced Chip-on-Lead Package

Figure 22.

Thermal Overload Protection

The ADP3330 is protected against damage due to excessive

power dissipation by its thermal overload protection circuit

which limits the die temperature to a maximum of +165

°C.

Under extreme conditions (i.e., high ambient temperature and

power dissipation) where die temperature starts to rise above

+165

°C, the output current is reduced until the die temperature

has dropped to a safe level. The output current is restored when

the die temperature is reduced.

Current and thermal limit protections are intended to protect

the device against accidental overload conditions. For normal

operation, device power dissipation should be externally limited

so that junction temperatures will not exceed +125

°C.

Calculating Junction Temperature

Device power dissipation is calculated as follows:

Where

and

Assuming

The proprietary package used in the ADP3330 has a thermal

resistance of 165

°C/W, significantly lower than a standard

6-lead SOT-23 package. Assuming a 4-layer board, the junction

temperature rise above ambient temperature will be approxi-

mately equal to:

∆T

J

× 165°C/W = 42.4°C

To limit the maximum junction temperature to +125

°C,

maximum allowable ambient temperature will be: