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ADSP-BF609 Arkusz danych(PDF) 9 Page - Analog Devices |
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ADSP-BF609 Arkusz danych(HTML) 9 Page - Analog Devices |
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9 / 112 page  Rev. 0 | Page 9 of 112 | June 2013 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Internal (Core-Accessible) Memory The L1 memory system is the highest-performance memory available to the Blackfin processor cores. Each core has its own private L1 memory. The modified Har- vard architecture supports two concurrent 32-bit data accesses along with an instruction fetch at full processor speed which provides high bandwidth processor performance. In each core a 64K-byte block of data memory partners with an 80K-byte memory block for instruction storage. Each data block is multi- banked for efficient data exchange through DMA and can be configured as SRAM. Alternatively, 16K bytes of each block can be configured in L1 cache mode. The four-way set-associative instruction cache and the 2 two-way set-associative data caches greatly accelerate memory access performance, especially when accessing external memories. The L1 memory domain also features a 4K-byte scratchpad SRAM block which is ideal for storing local variables and the software stack. All L1 memory is protected by a multi-parity bit concept, regardless of whether the memory is operating in SRAM or cache mode. Outside of the L1 domain, L2 and L3 memories are arranged using a Von Neumann topology. The L2 memory domain is a unified instruction and data memory and can hold any mixture of code and data required by the system design. The L2 memory domain is accessible by both Blackfin cores through a dedicated 64-bit interface. It operates at SYSCLK frequency. The processor features up to 256K bytes of L2 SRAM which is ECC-protected and organized in eight banks. Individual banks can be made private to any of the cores or the DMA subsystem. There is also a 32K-byte single-bank ROM in the L2 domain. It contains boot code and safety functions. Static Memory Controller (SMC) The SMC can be programmed to control up to four banks of external memories or memory-mapped devices, with very flexi- ble timing parameters. Each bank occupies a 64M byte segment regardless of the size of the device used, so that these banks are only contiguous if each is fully populated with 64M bytes of memory. Dynamic Memory Controller (DMC) The DMC includes a controller that supports JESD79-2E com- patible double data rate (DDR2) SDRAM and JESD209A low power DDR (LPDDR) SDRAM devices. I/O Memory Space The processor does not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On- chip I/O devices have their control registers mapped into mem- ory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Booting The processor has several mechanisms for automatically loading internal and external memory after a reset. The boot mode is defined by the SYS_BMODE input pins dedicated for this pur- pose. There are two categories of boot modes. In master boot modes, the processor actively loads data from parallel or serial memories. In slave boot modes, the processor receives data from external host devices. The boot modes are shown in Table 2. These modes are imple- mented by the SYS_BMODE bits of the reset configuration register and are sampled during power-on resets and software- initiated resets. VIDEO SUBSYSTEM The following sections describe the components of the proces- sor’s video subsystem. These blocks are shown with blue shading in Figure 1 on Page 1. Video Interconnect (VID) The Video Interconnect provides a connectivity matrix that interconnects the Video Subsystem: three PPIs, the PIXC, and the PVP. The interconnect uses a protocol to manage data transfer among these video peripherals. Pipelined Vision Processor (PVP) The PVP engine provides hardware implementation of signal and image processing algorithms that are required for co-processing and pre-processing of monochrome video frames in ADAS applications, robotic systems, and other machine applications. The PVP works in conjunction with the Blackfin cores. It is optimized for convolution and wavelet based object detection and classification, and tracking and verification algorithms. The PVP has the following processing blocks. • Four 5 × 5 16-bit convolution blocks optionally followed by down scaling • A 16-bit cartesian-to-polar coordinate conversion block • A pixel edge classifier that supports 1st and 2nd derivative modes • An arithmetic unit with 32-bit addition, multiply and divide Table 2. Boot Modes SYS_BMODE Setting Boot Mode 000 No boot/Idle 001 Memory 010 RSI0 Master 011 SPI0 Master 100 SPI0 Slave 101 Reserved 110 LP0 Slave 111 UART0 Slave |
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