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AD9726BSVZ Arkusz danych(PDF) 5 Page - Analog Devices |
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AD9726BSVZ Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 24 page AD9726 Rev. B | Page 5 of 24 DIGITAL SIGNAL SPECIFICATIONS DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, IOUT-FS = 20 mA, internal reference, TMIN to TMAX, unless otherwise specified. Table 3. Parameter Min Typ Max Unit DAC CLOCK INPUTS (CLK±) Differential Voltage 0.5 1.0 V Common-Mode Voltage 1.0 1.25 V LVDS INPUTS (DB[15:0]±, DCLK_IN±) Input Voltage Range 825 1575 mV Differential Threshold Voltage 100 mV Differential Input Impedance 100 Ω LVDS OUTPUT (DCLK_OUT±) Differential Output Voltage1 250 400 mV Offset Voltage 1.0 1.2 V Short-Circuit Output Current 20 mA CMOS INPUTS (CSB, SCLK, SDIO, RESET) Logic 0 Voltage 0.5 V Logic 1 Voltage 2.5 V Input Current 1 nA CMOS OUTPUTS (SDO, SDIO) Logic 0 Voltage 0.5 V Logic 1 Voltage 3.0 V Short-Circuit Output Current 10 mA CONTROL INPUTS (SPI_DIS, SDR_EN) Logic 0 Voltage 0.5 V Logic 1 Voltage 2.0 V Input Current 1 nA 1 With 100 Ω external load. TIMING SPECIFICATIONS DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, IOUT-FS = 20 mA, internal reference, TMIN to TMAX, unless otherwise specified. Table 4. Parameter Min Typ Max Unit LVDS DATA BUS Data Synchronization Enabled (Default) DDR DCLK_OUT± Propagation Delay (tDCPD-DDR) 2000 ps DDR DB[15:0]± Setup Time (tDSU-DDR) −100 ps DDR DB[15:0]± Hold Time (tDH-DDR) 500 ps SDR DCLK_OUT± Propagation Delay (tDCPD-SDR) 300 ps SDR DB[15:0]± Setup Time (tDSU-SDR) −100 ps SDR DB[15:0]± Hold Time (tDH-SDR) 500 ps Data Synchronization Bypassed DB[15:0]± Setup Time (tDSU-BYPASS) 800 ps DB[15:0]± Hold Time (tDH-BYPASS) 50 ps CLK± to IOUT Propagation Delay (tPD-BYPASS) 0.85 ns DB[15:0]± to IOUT Pipeline Delay (tPIPE-BYPASS) 4 DAC clock cycles |
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