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ADV7281WBCPZ Arkusz danych(PDF) 11 Page - Analog Devices |
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ADV7281WBCPZ Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 32 page Data Sheet ADV7281 Rev. A | Page 11 of 32 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 24 AIN3 23 DIAG2 22 DIAG1 21 AVDD 20 VREFN 19 VREFP 18 AIN2 17 AIN1 1 2 3 4 5 6 7 8 DGND DVDDIO DVDD DGND P7 P6 P5 P4 ADV7281 TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO DGND. Figure 7. Pin Configuration, ADV7281 Table 9. Pin Function Descriptions, ADV7281 Pin No. Mnemonic Type Description 1, 4 DGND Ground Ground for Digital Supply. 2 DVDDIO Power Digital I/O Power Supply (1.8 V or 3.3 V). 3, 13 DVDD Power Digital Power Supply (1.8 V). 5 to 12 P7 to P0 Output Video Pixel Output Ports. 14 XTALP Output Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7281. The crystal used with the ADV7281 must be a fundamental crystal. 15 XTALN Input Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7281must be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7281, the output of the oscillator is fed into the XTALN pin. 16 PVDD Power PLL Power Supply (1.8 V). 17, 18, 24, 25 AIN1 to AIN4 Input Analog Video Input Channels. 19 VREFP Output Internal Voltage Reference Output. 20 VREFN Output Internal Voltage Reference Output. 21 AVDD Power Analog Power Supply (1.8 V). 22 DIAG1 Input Diagnostic Input 1. 23 DIAG2 Input Diagnostic Input 2. 26 INTRQ Output Interrupt Request Output. An interrupt occurs when certain signals are detected on the input video. 27 RESET Input System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to reset the ADV7281 circuitry. 28 ALSB Input This pin selects the I2C write address for the ADV7281. When ALSB is set to Logic 0, the write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42. 29 SDATA Input/output I2C Port Serial Data Input/Output. 30 SCLK Input I2C Port Serial Clock Input. The maximum clock rate is 400 kHz. 31 PWRDWN Input Power-Down Pin. A logic low on this pin places the ADV7281 in power-down mode. 32 LLC Output Line-Locked Output Clock for Output Pixel Data. The clock output is nominally 27 MHz, but it increases or decreases according to the video line length. EPAD (EP) Exposed Pad. The exposed pad must be connected to DGND. |
Podobny numer części - ADV7281WBCPZ |
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Podobny opis - ADV7281WBCPZ |
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