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AD7892AN-1 Arkusz danych(PDF) 10 Page - Analog Devices |
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AD7892AN-1 Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 14 page AD7892 –10– REV. C pulse can be applied to the CS and RD inputs to latch data out of the AD7892 and into the gate array or ASIC. This eliminates the logic required in the gate array or ASIC to recognize the end of conversion and generate the read signal for the AD7892. To obtain optimum performance from the AD7892, it is not recom- mended to tie CS and RD permanently low as this keeps the three-state active during conversion. Serial Interface Mode The AD7892 is configured for serial mode interfacing by tying the MODE input low. It provides for a three-wire, serial link between the AD7892 and industry-standard microprocessors, microcontrollers and digital signal processors. SCLK and RFS of the AD7892 are inputs, and the AD7892’s serial interface is designed for direct interface to systems that provide a serial clock input that is synchronized to the serial data output includ- ing microcontrollers such as the 80C51, 87C51, 68HC11 and 68HC05 and most digital signal processors. Figure 3 shows the timing diagram for reading from the AD7892 in the serial interface mode. RFS goes low to access data from the AD7892. The serial clock input does not have to be con- tinuous. The serial data can be accessed in a number of bytes. However, RFS must remain low for the duration of the data transfer operation. Sixteen bits of data are transmitted with four leading zeros followed by the 12-bit conversion result starting with the MSB. Serial data is clocked out of the device on the rising edge of SCLK. Old data is guaranteed to be valid for 5 ns after this edge. This is useful for high speed serial clocks where the access time of the part would not allow sufficient set-up time for the data to be accepted on the falling edge of the clock. In this case, care must be taken that RFS does not go just prior to a rising edge of SCLK. For slower serial clocks data is valid on the falling edge of SCLK. At the end of the read operation, the SDATA line is three-stated by a rising edge on either the SCLK or RFS inputs, whichever occurs first. Serial data cannot be read during conversion to avoid feedthrough problems from the serial clock to the conversion process. For optimum perfor- mance of the AD7892-3, a serial read should also be avoided within 200 ns of the rising edge of CONVST to avoid feedthrough into the track/hold during its acquisition time. The serial read should, therefore, occur between the end of conversion ( EOC falling edge) and 200 ns prior to the next rising edge of CONVST. For the AD7892-1 and AD7892-2, a serial read should also be avoided within 400 ns of the rising edge of CONVST. This limits the maximum achievable throughput rate in serial mode (assuming 20 MHz serial clock) to 400 kSPS for the AD7892-3 and 357 kSPS for the AD7892-1 and AD7892-2. Analog Input Section The AD7892 is offered as three part types allowing for four different analog input voltage ranges. The AD7892-1 handles either ± 5 V or ± 10 V input voltage ranges. The AD7892-2 handles a 0 V to +2.5 V input voltage range while the AD7892-3 handles an input range of ±2.5 V. AD7892-1 Figure 4 shows the analog input section for the AD7892-1. The analog input range is pin-strappable (using VIN2) for either ±5V or ±10 V on the VIN1 input. With VIN2 connected to AGND, the input range on VIN1 is ±10 V, and the input resistance on VIN1 is 15 k Ω nominal. With V IN2 connected to VIN1, the input range on VIN1 is ±5 V, and the input resistance on VIN1 is 8 kΩ nominal. As a result, the VIN1 and VIN2 inputs should be driven from a low impedance source. The resistor attenuator stage is followed by the high input impedance stage of the track/hold amplifier. This resistor attenuator stage allows the input voltage to go to ±17 V without damaging the AD7892-1. +2.5 REFERENCE REF OUT/ REF IN VIN1 VIN2 AGND TO HIGH IMPEDANCE SHA INPUT TO ADC REFERENCE CIRCUITRY 2k 3.25k 13k 6.5k 13k Figure 4. AD7892-1 Analog Input Structure t13 t10 THREE- STATE RFS (I) SCLK (I) SDATA (O) NOTE: I = INPUT; O = OUTPUT FOUR LEADING ZEROS t12 t11 t16 t17 t17A t14 DB11 DB10 DB0 t15 Figure 3. Serial Mode Timing Diagram |
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