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AD8321 Arkusz danych(PDF) 3 Page - Analog Devices |
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AD8321 Arkusz danych(HTML) 3 Page - Analog Devices |
3 / 20 page AD8321 LOGIC INPUTS (TTL/CMOS Logic) (DATEN, CLK, SDATA, V CC = +9 V; Full Temperature Range) Parameter Min Typ Max Unit Logic “1” Voltage Logic “0” Voltage Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN Logic “1” Current (VINH = 5 V) PD Logic “0” Current (VINL = 0 V) PD 2.1 0 0 –600 50 –250 5.0 0.8 20 –100 190 –30 V V nA nA mA mA TIMING REQUIREMENTS (Full Temperature Range, V CC = +9 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.) Parameter Min Typ Max Unit Clock Pulsewidth (TWH) Clock Period (TC) Setup Time SDATA vs. Clock (TDS) Setup Time DATEN vs. Clock (T ES) Hold Time SDATA vs. Clock (TDH) Hold Time DATEN vs. Clock (T EH) Input Rise and Fall Times, SDATA, DATEN, Clock (T R, TF) 16.0 32.0 5.0 15.0 5.0 3.0 10 ns ns ns ns ns ns ns Specifications subject to change without notice. TES VALID DATA WORD G1 MSB. . . .LSB GAIN TRANSFER (G1) TDS TEH 8 CLOCK CYCLES GAIN TRANSFER (G2) TOFF TGS ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) PD PEDESTAL CLK SDATA DATEN TON TC TWH VALID DATA WORD G2 Figure 2. Serial Interface Timing VALID DATA BIT MSB MSB-1 MSB-2 TDS TDH SDATA CLK Figure 3. SDATA Timing REV. A –3– |
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