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AD9831 Arkusz danych(PDF) 11 Page - Analog Devices |
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AD9831 Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 16 page AD9831 –11– MCLK cycle introduced otherwise. When these inputs change value, there will be a pipeline delay before control is transferred to the selected register—there will be a pipeline delay before the analog output is controlled by the selected register. There is a similar delay when a new word is written to a register. PSEL0, PSEL1, FSELECT and WR have latencies of six MCLK cycles. The flow chart in Figure 22 shows the operating routine for the AD9831. When the AD9831 is powered up, the part should be reset using RESET. This will reset the phase accumulator to zero so that the analog output is at midscale. RESET does not reset the phase and frequency registers. These registers will contain invalid data and, therefore, should be set to zero by the user. The registers to be used should be loaded, the analog output being fMCLK/2 32 × FREG where FREG is the value loaded into the selected frequency register. This signal will be phase shifted by the amount specified in the selected phase register (2 π/4096 × PHASEREG where PHASEREG is the value contained in the selected phase register). When FSELECT, PSEL0 and PSEL1 are programmed, there will be a pipeline delay of approximately 6 MCLK cycles before the analog output reacts to the change on these inputs. DATA WRITE FREG<0, 1> = 0 PHASEREG<0, 1, 2, 3> = 0 DATA WRITE FREG<0> = fOUT0/fMCLK*2 32 FREG<1> = fOUT1/fMCLK*2 32 SELECT DATA SOURCES SET FSELECT SET PSEL0, PSEL1 DAC OUTPUT VOUT = VREFIN*6.25*ROUT/RSET*(1 + SIN(2π(FREG*fMCLK*t/232 + PHASEREG/212))) WAIT 6 MCLK CYCLES CHANGE PHASE? CHANGE FOUT? CHANGE FREG? YES CHANGE PHASEREG? CHANGE PSEL0, PSEL1 YES NO NO YES NO YES NO RESET PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3> CHANGE FSELECT Figure 22. Flow Chart for AD9831 Initialization and Operation DSP and MPU Interfacing The AD9831 has a parallel interface, with 16 bits of data being loaded during each write cycle. The frequency or phase registers are loaded by asserting the WR signal. The destination register for the 16 bit data is selected using the address inputs A0, A1 and A2. The phase registers are 12 bits wide so, only the 12 LSBs need to be valid—the 4 MSBs of the 16 bit word do not have to contain valid data. Data is loaded into the AD9831 by pulsing WR low, the data being latched into the AD9831 on the rising edge of WR. The values of inputs A0, A1 and A2 are also latched into the AD9831 on the WR rising edge. The appropriate destination register is updated on the next MCLK rising edge. If the WR rising edge coincides with the MCLK rising edge, there is an uncertainty of one MCLK cycle regarding the loading of the destination register—the destination register may be loaded immediately or the destination register may be updated on the next MCLK rising edge. To avoid any uncertainty, the times listed in the specifications should be complied with. FSELECT, PSEL0 and PSEL1 are sampled on the MCLK rising edge. Again, these inputs should be valid when an MCLK rising edge occurs as there will be an uncertainty of one REV. B |
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Podobny opis - AD9831 |
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