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AD9861BCPZ-50 Arkusz danych(PDF) 3 Page - Analog Devices |
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AD9861BCPZ-50 Arkusz danych(HTML) 3 Page - Analog Devices |
3 / 52 page AD9861 Rev. 0 | Page 3 of 52 Tx PATH SPECIFICATIONS Table 1. AD9861-50 and AD9861-80 FDAC = 200 MSPS; 4× interpolation; RSET = 4.02 kΩ; differential load resistance of 100 Ω1; TxPGA = 20 dB, AVDD = DVDD = 3.3 V, unless otherwise noted Parameter Temp Test Level Min Typ Max Unit Tx PATH GENERAL Resolution Full IV 10 Bits Maximum DAC Update Rate Full IV 200 MHz Maximum Full-Scale Output Current Full IV 20 mA Full-Scale Error Full V 1% Gain Mismatch Error 25°C IV –3.5 +3.5 % FS Offset Mismatch Error Full IV –0.1 +0.1 % FS Reference Voltage Full V 1.23 V Output Capacitance Full V 5 pF Phase Noise (1 kHz Offset, 6 MHz Tone) 25°C V –115 dBc/Hz Output Voltage Compliance Range Full IV –1.0 +1.0 V TxPGA Gain Range Full V 20 dB TxPGA Step Size Full V 0.10 dB Tx PATH DYNAMIC PERFORMANCE (IOUTFS = 20 mA; FOUT = 1 MHz) SNR Full IV 60.2 60.8 dB SINAD Full IV 59.7 60.7 dB THD Full IV −77.5 −65.8 dBc SFDR, Wideband (DC to Nyquist) Full IV 64.6 76.0 dBc SFDR, Narrowband (1 MHz Window) Full IV 72.5 81.0 dBc 1 See Figure 2 for description of the TxDAC termination scheme. 03606-0-030 TxDAC 50 Ω 50 Ω Figure 2. Diagram Showing Termination of 100 Ω Differential Load for Some TxDAC Measurements |
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Podobny opis - AD9861BCPZ-50 |
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