Zakładka z wyszukiwarką danych komponentów |
|
AD9833BRM Arkusz danych(PDF) 4 Page - Analog Devices |
|
AD9833BRM Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 24 page AD9833 Data Sheet Rev. E | Page 4 of 24 TIMING CHARACTERISTICS VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.1 Table 2. Parameter Limit at T MIN to TMAX Unit Description t 1 40 ns min MCLK period t 2 16 ns min MCLK high duration t 3 16 ns min MCLK low duration t 4 25 ns min SCLK period t 5 10 ns min SCLK high duration t 6 10 ns min SCLK low duration t 7 5 ns min FSYNC to SCLK falling edge setup time t 8 min 10 ns min FSYNC to SCLK hold time t 8 max t 4 − 5 ns max t 9 5 ns min Data setup time t 10 3 ns min Data hold time t 11 5 ns min SCLK high to FSYNC falling edge setup time 1 Guaranteed by design, not production tested. Timing Diagrams t2 t1 MCLK t3 Figure 3. Master Clock t5 t4 t6 t7 t8 t10 t9 4 1 D 5 1 D D0 D1 D2 D14 SCLK FSYNC SDATA D15 t11 Figure 4. Serial Timing |
Podobny numer części - AD9833BRM |
|
Podobny opis - AD9833BRM |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |