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ADIS16201 Arkusz danych(PDF) 4 Page - Analog Devices |
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ADIS16201 Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 32 page ADIS16201 Data Sheet Rev. C | Page 4 of 32 Parameter Conditions Min Typ Max Unit DAC OUTPUT 5 kΩ/100 pF to GND Resolution 12 Bits Relative Accuracy For Code 101 to Code 4095 4 LSB Differential Nonlinearity 1 LSB Offset Error ±5 mV Gain Error ±0.5 % Output Range 0 to 2.5 V Output Impedance 2 Ω Output Settling Time 10 µs LOGIC INPUTS Input High Voltage, VINH 2.0 V Input Low Voltage, VINL 0.8 V Logic 1 Input Current, IINH VIH = VDD ±0.2 ±1 µA Logic 0 Input Current, IINL VIL = 0 V −40 −60 μA Input Capacitance, CIN 10 pF DIGITAL OUTPUTS Output High Voltage, VOH ISOURCE = 1.6 mA 2.4 V Output Low Voltage, VOL ISINK = 1.6 mA 0.4 V SLEEP TIMER Timeout Period3 0.5 128 Seconds FLASH MEMORY Endurance4 20,000 Cycles Data Retention5 TJ = 85°C 20 Years CONVERSION RATE Minimum Conversion Time 244 μs Maximum Conversion Time 484 ms Maximum Throughput Rate 4096 SPS Minimum Throughput Rate 2.066 SPS POWER SUPPLY Operating Voltage Range VDD 3.0 3.3 3.6 V Power Supply Current Normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz), at 25°C 11 14 mA Fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz), at 25°C 36 42 mA Sleep mode, at 25°C 500 750 µA Turn-On Time6 130 ms 1 Guaranteed by iMEMs packaged part testing, design, and/or characterization. 2 Self-test response changes as the square of VDD. 3 Guaranteed by design. 4 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 5 Retention lifetime equivalent at junction temperature (TJ) 85°C as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature. 6 The start-up time defines the time from VDD > 3.0 V to the first output register update. This parameter does not account for filter settling, which depends on the SMPL_PRD and AVG_CNT settings. |
Podobny numer części - ADIS16201 |
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Podobny opis - ADIS16201 |
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