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ADS5520IPAPRG4 Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADS5520IPAPRG4 Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 38 page TIMING CHARACTERISTICS (1) (2) ADS5520 www.ti.com....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008 Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF, unless otherwise noted PARAMETER DESCRIPTION MIN TYP MAX UNIT Switching Specification Aperture delay, tA Input CLK falling edge to data sampling point 1 ns Aperture jitter (uncertainty) Uncertainty in sampling instant 300 fs Data setup time, tSU Data valid(3) to 50% of CLKOUT rising edge 2.3 2.7 ns Data hold time, tH 50% of CLKOUT rising edge to data becoming 1.7 2 ns invalid(3) Input clock to output data valid start, Input clock rising edge to data valid start delay 2 2.6 ns tSTART (4) (5) Input clock to output data valid end, Input clock rising edge to data valid end delay 5.8 6.9 ns tEND (4) (5) Output clock jitter, tJIT Uncertainty in CLKOUT rising edge, peak-to-peak 150 210 psPP Output clock rise time, tr Rise time of CLKOUT from 20% to 80% of DRVDD 1.7 1.9 ns Output clock fall time, tf Fall time of CLKOUT from 80% to 20% of DRVDD 1.5 1.7 ns Input clock to output clock delay, tPDI Input clock rising edge, zero crossing, to output 4.2 4.8 5.5 ns clock rising edge 50% Data rise time, tr Data rise time measured from 20% to 80% of 3.6 4.6 ns DRVDD Data fall time, tf Data fall time measured from 80% to 20% of 2.8 3.7 ns DRVDD Output enable(OE) to data output delay Time required for outputs to have stable timings 1000 Clock with regard to input clock(6) after OE is activated cycles Time to valid data after coming out of software 1000 power down Clock Wake-up time cycles Time to valid data after stopping and restarting the 1000 clock Latency Time for a sample to propagate to the ADC outputs 17.5 Clock cycles (1) Timing parameters are ensured by design and characterization, and not tested in production. (2) See Table 6 through Table 9 in the Application Information section for timing information at additional sampling frequencies. (3) Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW. (4) See the Output Information section for details on using the input clock for data capture. (5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3). Add 1/2 clock period for the valid number for a falling edge CLKOUT polarity. (6) Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect to input clock. Copyright © 2004–2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS5520 |
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