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AD9559BCPZ Arkusz danych(PDF) 11 Page - Analog Devices |
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AD9559BCPZ Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 120 page Data Sheet AD9559 Rev. 0 | Page 11 of 120 SERIAL PORT SPECIFICATIONS—SPI MODE Table 14. Parameter Min Typ Max Unit Test Conditions/Comments M5/ EE CS M5/ A CSE A is a dual function pin; the values in this table apply when this pin is used as a serial port pin, that is, A CSEE A ; see Table 16 for the specifications when this pin is used as a multifunction pin (M5) Input Logic 1 Voltage 2.2 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 20 µA Input Logic 0 Current 50 µA Input Capacitance 2 pF SCLK Internal 10 kΩ pull-down resistor Input Logic 1 Voltage 2.2 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 200 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF SDIO As an Input Input Logic 1 Voltage 2.2 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 1 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF As an Output Output Logic 1 Voltage VDD3 − 0.6 V 1 mA load current Output Logic 0 Voltage 0.4 V 1 mA load current M4/SDO M4/SDO is a dual function pin; the values in this table apply when this pin is used as a serial port pin, that is SDO; see Table 16 for the specifications when this pin is used as a multifunction pin (M4) Output Logic 1 Voltage VDD3 − 0.6 V 1 mA load current Output Logic 0 Voltage 0.4 V 1 mA load current TIMING See Figure 47 and Figure 50 SCLK Clock Rate, 1/tCLK 40 MHz Pulse Width High, tHIGH 10 ns Pulse Width Low, tLOW 13 ns SDIO to SCLK Setup, tDS 3 ns SCLK to SDIO Hold, tDH 6 ns SCLK to Valid SDIO and SDO, tDV 10 ns AA CSEE AA to SCLK Setup (tS) 10 ns AA CSEE AA to SCLK Hold (tC) 0 ns AA CSEE AA Minimum Pulse Width High 6 ns |
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