LC87F1K64A

No.A2197-5/35

• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.

1) Oscillators do not stop automatically.

2) There are three ways of releasing HOLD mode.

(1) Setting the reset pin to a low level.

(2) Generating a reset signal by watchdog timer or low-voltage detection

(3) Occurrence of an interrupt

• HOLD mode: Suspends instruction execution and operation of the peripheral circuits.

1) The PLL, CF, RC and crystal oscillators automatically stop operation.

Note: Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in standby mode

is also controlled.

2) There are five ways of releasing HOLD mode.

(1) Setting the reset pin to a low level

(2) Generating a reset signal by the watchdog timer or low-voltage detection

(3) Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins

* INT0 and INT1 HOLD mode release is available only when level detection is configured.

(4) Establishing an interrupt source at port 0

(5) Establishing an bus active interrupt source in the USB host control circuit

• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer

and infrared remote control receiver circuit.

1) The PLL, CF and RC oscillators automatically stop operation.

Note: Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in standby mode

is also controlled.

Note: The low-speed RC oscillator retains the state that is established on entry into X'tal HOLD mode if the base

timer is running with the low-speed RC oscillator selected as the base timer input clock source.

2) The state of crystal oscillator established when the X'tal HOLD mode is entered is retained.

3) There are seven ways of releasing X'tal HOLD mode.

(1) Setting the reset pin to a low level

(2) Generating a reset signal by the watchdog timer or low-voltage detection

(3) Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins

* INT0 and INT1 X'tal HOLD mode release is available only when level detection is configured.

(4) Establishing an interrupt source at port 0

(5) Establishing an interrupt source in the base timer circuit

(6) Establishing an interrupt source in the infrared remote control receiver circuit

(7) Establishing an bus active interrupt source in the USB host control circuit

• On-chip debugger: TCB87–Type B + LC87F1K64A or

TCB87–Type C (3-wire communication cable) + LC87F1K64A

Package

Programming Board

SQFP48 (7×7)

W87F55256SQ