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74AUP1G02GS Arkusz danych(PDF) 8 Page - NXP Semiconductors |
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74AUP1G02GS Arkusz danych(HTML) 8 Page - NXP Semiconductors |
8 / 21 page 74AUP1G02 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 27 June 2012 8 of 21 NXP Semiconductors 74AUP1G02 Low-power 2-input NOR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9 Symbol Parameter Conditions Min Typ [1] Max Unit Tamb = 25 °C; CL = 5 pF tpd propagation delay A, B to Y; see Figure 8 [2] VCC = 0.8 V - 17.0 - ns VCC = 1.1 V to 1.3 V 2.5 5.1 10.8 ns VCC = 1.4 V to 1.6 V 1.6 3.7 6.7 ns VCC = 1.65 V to 1.95 V 1.3 3.0 5.3 ns VCC = 2.3 V to 2.7 V 1.0 2.4 3.9 ns VCC = 3.0 V to 3.6 V 1.0 2.2 3.4 ns Tamb = 25 °C; CL = 10 pF tpd propagation delay A, B to Y; see Figure 8 [2] VCC = 0.8 V - 20.4 - ns VCC = 1.1 V to 1.3 V 2.4 6.0 12.8 ns VCC = 1.4 V to 1.6 V 1.9 4.3 7.9 ns VCC = 1.65 V to 1.95 V 1.6 3.6 6.2 ns VCC = 2.3 V to 2.7 V 1.4 3.0 4.7 ns VCC = 3.0 V to 3.6 V 1.3 2.7 4.2 ns Tamb = 25 °C; CL = 15 pF tpd propagation delay A, B to Y; see Figure 8 [2] VCC = 0.8 V - 23.9 - ns VCC = 1.1 V to 1.3 V 3.4 6.8 14.6 ns VCC = 1.4 V to 1.6 V 2.3 4.8 8.9 ns VCC = 1.65 V to 1.95 V 1.9 4.0 7.0 ns VCC = 2.3 V to 2.7 V 1.7 3.4 5.4 ns VCC = 3.0 V to 3.6 V 1.6 3.2 4.8 ns Tamb = 25 °C; CL = 30 pF tpd propagation delay A, B to Y; see Figure 8 [2] VCC = 0.8 V - 34.2 - ns VCC = 1.1 V to 1.3 V 4.6 9.0 19.9 ns VCC = 1.4 V to 1.6 V 3.4 6.4 11.8 ns VCC = 1.65 V to 1.95 V 2.6 5.3 9.3 ns VCC = 2.3 V to 2.7 V 2.4 4.5 7.1 ns VCC = 3.0 V to 3.6 V 2.3 4.2 6.4 ns |
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