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Si5376B-A-BL Arkusz danych(PDF) 1 Page - Silicon Laboratories |
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Si5376B-A-BL Arkusz danych(HTML) 1 Page - Silicon Laboratories |
1 / 66 page Rev. 1.0 9/12 Copyright © 2012 by Silicon Laboratories Si5376 Si5376 4-PLL A NY-F REQUENCY P RECISION C LOCK M ULTIPLIER/J ITTER A TTENUATOR Features Applications Description The Si5376 is a highly-integrated, 4-PLL, jitter-attenuating precision clock multiplier for applications requiring sub-1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts two input clocks ranging from 2 kHz to 710 MHz and generates two independent synchronous output clocks ranging from 2 kHz to 808 MHz. The device provides virtually any frequency translation combination across this operating range. For asynchronous, free-running clock generation applications, the Si5376’s reference oscillator can be used as a clock source for any of the four DSPLLs. The Si5376 input clock frequency and clock multiplication ratio are programmable through an I2C interface. The Si5376 is based on Silicon Laboratories’ third-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly-integrated PLL solution that eliminates the need for external VCXO and loop filter components. Each DSPLL loop bandwidth is digitally-programmable, providing jitter performance optimization at the application level. The device operates from a single 1.8 or 2.5 V supply with on-chip voltage regulators with excellent PSRR. The Si5376 is ideal for providing clock multiplication and jitter attenuation in high-port-count optical line cards requiring independent timing domains. Highly-integrated, 4 PLL clock multiplier/jitter attenuator Four independent DSPLLs support any-frequency synthesis and jitter attenuation 8 inputs/8 outputs Each DSPLL can generate any frequency from 2 kHz to 808 MHz from a 2 kHz to 710 MHz input 350 fs rms (12 kHz– 20 MHz) and 410 fs rms (50 kHz–80 MHz) typical Meets ITU-T G.8251 and Telcordia GR-253-CORE OC-192 jitter specifications Programmable loop bandwidth: 60 Hz to 8 kHz Faster lock acquisition compared to the Si5374: <1.2 s For a very low-loop BW version, see the Si5374 Supports all ITU G.709 and any custom FEC ratios (239/237, 255/238, 255/237, 255/236, 253/226) Integrated loop filter with programmable bandwidth Simultaneous free-run and synchronous operation Automatic/manual hitless input clock switching Selectable output clock signal format (LVPECL, LVDS, CML, CMOS) LOL and interrupt alarm outputs I2C programmable Single 1.8 V ±5% or 2.5 V ±10% operation with high PSRR on-chip voltage regulator 10x10 mm PBGA High-density, any-port, any-protocol, any-frequency line cards ITU-T G.709 OTN custom FEC 10/40/100G OC-48/192, STM-16/64 1/2/4/8/10G Fibre Channel GbE/10 GbE Synchronous Ethernet Carrier Ethernet, multi-service switches and routers MSPP, ROADM, P-OTS, muxponders Ordering Information: See page 61. |
Podobny numer części - Si5376B-A-BL |
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Podobny opis - Si5376B-A-BL |
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