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AD1858JRSRL Arkusz danych(PDF) 11 Page - Analog Devices |
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AD1858JRSRL Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 16 page AD1857/AD1858 REV. 0 –11– LEFT CHANNEL RIGHT CHANNEL BCLK INPUT SDATA INPUT LRCLK INPUT MSB MSB-1 LSB+2 LSB+1 LSB MSB-1 LSB+2 LSB+1 LSB MSB MSB-1 MSB Figure 12. AD1858 Left-Justified DSP Serial Port Style LEFT CHANNEL RIGHT CHANNEL BCLK INPUT SDATA INPUT LRCLK INPUT MSB MSB-1 LSB+2 LSB+1 LSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 LSB MSB-2 MSB Figure 13. AD1857/AD1858 32 FS Packed Mode Figure 12 shows the AD1858 left-justified DSP serial port style mode. L RCLK must pulse HI for at least one bit clock period before the MSB of the left channel is valid, and L RCLK must pulse HI again for at least one bit clock period before the MSB of the right channel is valid. Data is valid on the falling edge of BCLK. Note that in this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first L RCLK pulse, the right data is transmitted with the second L RCLK pulse, and synchronism is maintained from that point forward. Note that in 16-bit input mode, the AD1857/AD1858 are capable of a 32 × F S BCLK frequency “packed mode” where the MSB is left-justified to an L RCLK transition, and the LSB is right-justified to an L RCLK transition. LRCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. Packed mode can be used when the AD1857 is programmed in left-justified mode, or when the AD1858 is programmed in right-justified mode. Packed mode is shown in Figure 13. Master Clock The synchronous master clock of the AD1857/AD1858 is supplied by an external clock source applied to MCLK. Figure 14 shows example connections. Do not change the state of the 384/ 256 pin while the AD1857/AD1858 is operational; this pin should be hardwired LO or HI. Alternatively, its state may be changed while the PD/RST pin is asserted LO. 1 MCLK 6 256 MODE 384 MODE SAMPLE RATE 12.288MHz 18.432MHz 48kHz 44.1kHz 32kHz 11.2896MHz 16.9344MHz 8.192MHz 12.288MHz 384/256 MCLK FREQUENCY 384/256 = LO 384/256 = HI Figure 14. AD1857/AD1858 Clock Connections Digital Mute The AD1857/AD1858 offer a control pin that mutes the analog output. By asserting the MUTE (Pin 15) signal HI, both the left channel and the right channel are muted. The AD1857/ AD1858 have been designed to minimize pops and clicks when muting and unmuting the device. The AD1857/AD1858 include a zero crossing detector which attempts to implement mute on waveform zero crossings only. If a zero crossing is not found within 1024 input sample periods (approximately 23 milliseconds at 44.1 kHz), the output is muted regardless. Output Drive, Buffering and Loading The AD1857/AD1858 analog output stage is able to drive a 2 k Ω load. If lower impedance loads must be driven, an external buffer stage such as the Analog Devices SSM2142 should be used. The analog output is generally ac coupled with a 10 µF capacitor as shown in Figure 21. It is possible to dc couple the AD1857/AD1858 output into an op amp stage using the CMOUT signal as a bias point. On-Chip Voltage Reference The AD1857/AD1858 include an on-chip voltage reference that establishes the output voltage range. The nominal value of this reference is +2.25 V, which corresponds to a line output voltage swing of 3 V p-p. The line output signal is centered around a voltage established by the CMOUT (common-mode output) (Pin 10). The reference must be bypassed both on the FILT input (Pin 11) with 10 µF and 0.1 µF capacitors, and on the CMOUT output (Pin 10) with 10 µF and 0.1 µF capacitors, as shown in Figure 21. Both the FILT pin and the CMOUT pin use the AGND ground. The on-chip voltage reference may be overdriven with an external reference source by applying this voltage to the FILT pin. CMOUT and FILT must still be bypassed as shown in Figure 21. An external reference can be useful to calibrate multiple AD1857/AD1858 DACs to the same gain. Reference bypass capacitors larger than those suggested can be used to improve the signal-to-noise performance of the AD1857/AD1858. Power-Down and Reset The PD/RST input (Pin 2) is used to control the power consumed by the AD1857/AD1858. When PD/RST is held LO, the AD1857/AD1858 are placed in a low dissipation power-down state. When PD/RST is brought HI, the AD1857/AD1858 become ready for normal operation. The master clock (MCLK, Pin 1) must be running for a successful reset or power-down operation to occur. The PD/RST signal must be LO for a minimum of four master clock periods (326 ns with a 12.288 MHz MCLK frequency). When the PD/RST input (Pin 2) is brought HI, the AD1857/ AD1858 are reset. All registers in the AD1857/AD1858 digital engine (serial data port, interpolation filter and modulator) are zeroed, and the amplifiers in the analog section are shorted during the reset operation. The AD1857/AD1858 have been designed to minimize pops and clicks when entering and exiting the power-down state. |
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