Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

AD1858JRSRL Arkusz danych(PDF) 11 Page - Analog Devices

Numer części AD1858JRSRL
Szczegółowy opis  Stereo, Single Supply 16-, 18- and 20-Bit Sigma-Delta DACs
Download  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD1858JRSRL Arkusz danych(HTML) 11 Page - Analog Devices

Back Button AD1858JRSRL Datasheet HTML 7Page - Analog Devices AD1858JRSRL Datasheet HTML 8Page - Analog Devices AD1858JRSRL Datasheet HTML 9Page - Analog Devices AD1858JRSRL Datasheet HTML 10Page - Analog Devices AD1858JRSRL Datasheet HTML 11Page - Analog Devices AD1858JRSRL Datasheet HTML 12Page - Analog Devices AD1858JRSRL Datasheet HTML 13Page - Analog Devices AD1858JRSRL Datasheet HTML 14Page - Analog Devices AD1858JRSRL Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 16 page
background image
AD1857/AD1858
REV. 0
–11–
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LRCLK
INPUT
MSB
MSB-1
LSB+2
LSB+1
LSB
MSB-1
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB
Figure 12. AD1858 Left-Justified DSP Serial Port Style
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LRCLK
INPUT
MSB
MSB-1
LSB+2
LSB+1
LSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
LSB
MSB-2
MSB
Figure 13. AD1857/AD1858 32
FS Packed Mode
Figure 12 shows the AD1858 left-justified DSP serial port style
mode. L
RCLK must pulse HI for at least one bit clock period
before the MSB of the left channel is valid, and L
RCLK must
pulse HI again for at least one bit clock period before the MSB
of the right channel is valid. Data is valid on the falling edge of
BCLK. Note that in this mode, it is the responsibility of the DSP
to ensure that the left data is transmitted with the first L
RCLK
pulse, the right data is transmitted with the second L
RCLK pulse,
and synchronism is maintained from that point forward.
Note that in 16-bit input mode, the AD1857/AD1858 are
capable of a 32
× F
S BCLK frequency “packed mode” where
the MSB is left-justified to an L
RCLK transition, and the LSB
is right-justified to an L
RCLK transition. LRCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. Packed mode can be used when the
AD1857 is programmed in left-justified mode, or when the
AD1858 is programmed in right-justified mode. Packed mode
is shown in Figure 13.
Master Clock
The synchronous master clock of the AD1857/AD1858 is
supplied by an external clock source applied to MCLK. Figure
14 shows example connections. Do not change the state of the
384/
256 pin while the AD1857/AD1858 is operational; this pin
should be hardwired LO or HI. Alternatively, its state may be
changed while the
PD/RST pin is asserted LO.
1
MCLK
6
256 MODE
384 MODE
SAMPLE RATE
12.288MHz
18.432MHz
48kHz
44.1kHz
32kHz
11.2896MHz
16.9344MHz
8.192MHz
12.288MHz
384/256
MCLK FREQUENCY
384/256 = LO
384/256 = HI
Figure 14. AD1857/AD1858 Clock Connections
Digital Mute
The AD1857/AD1858 offer a control pin that mutes the analog
output. By asserting the MUTE (Pin 15) signal HI, both the
left channel and the right channel are muted. The AD1857/
AD1858 have been designed to minimize pops and clicks when
muting and unmuting the device. The AD1857/AD1858
include a zero crossing detector which attempts to implement
mute on waveform zero crossings only. If a zero crossing is not
found within 1024 input sample periods (approximately 23
milliseconds at 44.1 kHz), the output is muted regardless.
Output Drive, Buffering and Loading
The AD1857/AD1858 analog output stage is able to drive a 2 k
load. If lower impedance loads must be driven, an external
buffer stage such as the Analog Devices SSM2142 should be
used. The analog output is generally ac coupled with a 10
µF
capacitor as shown in Figure 21. It is possible to dc couple the
AD1857/AD1858 output into an op amp stage using the
CMOUT signal as a bias point.
On-Chip Voltage Reference
The AD1857/AD1858 include an on-chip voltage reference that
establishes the output voltage range. The nominal value of this
reference is +2.25 V, which corresponds to a line output voltage
swing of 3 V p-p. The line output signal is centered around a
voltage established by the CMOUT (common-mode output)
(Pin 10). The reference must be bypassed both on the FILT
input (Pin 11) with 10
µF and 0.1 µF capacitors, and on the
CMOUT output (Pin 10) with 10
µF and 0.1 µF capacitors, as
shown in Figure 21. Both the FILT pin and the CMOUT pin
use the AGND ground. The on-chip voltage reference may be
overdriven with an external reference source by applying this
voltage to the FILT pin. CMOUT and FILT must still be
bypassed as shown in Figure 21. An external reference can be
useful to calibrate multiple AD1857/AD1858 DACs to the same
gain. Reference bypass capacitors larger than those suggested
can be used to improve the signal-to-noise performance of the
AD1857/AD1858.
Power-Down and Reset
The
PD/RST input (Pin 2) is used to control the power consumed
by the AD1857/AD1858. When
PD/RST is held LO, the
AD1857/AD1858 are placed in a low dissipation power-down
state. When
PD/RST is brought HI, the AD1857/AD1858
become ready for normal operation. The master clock (MCLK,
Pin 1) must be running for a successful reset or power-down
operation to occur. The
PD/RST signal must be LO for a
minimum of four master clock periods (326 ns with a 12.288 MHz
MCLK frequency).
When the
PD/RST input (Pin 2) is brought HI, the AD1857/
AD1858 are reset. All registers in the AD1857/AD1858 digital
engine (serial data port, interpolation filter and modulator) are
zeroed, and the amplifiers in the analog section are shorted
during the reset operation. The AD1857/AD1858 have been
designed to minimize pops and clicks when entering and exiting
the power-down state.


Podobny numer części - AD1858JRSRL

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Analog Devices
AD1858JRSRL AD-AD1858JRSRL Datasheet
263Kb / 16P
   Stereo, Single Supply 16-, 18- and 20-Bit Sigma-Delta DACs
REV. 0
More results

Podobny opis - AD1858JRSRL

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Analog Devices
AD1858 AD-AD1858_15 Datasheet
266Kb / 16P
   Stereo, Single Supply 16-, 18- and 20-Bit Sigma-Delta DACs
REV. 0
AD1857 AD-AD1857 Datasheet
263Kb / 16P
   Stereo, Single Supply 16-, 18- and 20-Bit Sigma-Delta DACs
REV. 0
AD1857 AD-AD1857_15 Datasheet
266Kb / 16P
   Stereo, Single Supply 16-, 18- and 20-Bit Sigma-Delta DACs
REV. 0
logo
STMicroelectronics
TDA7535 STMICROELECTRONICS-TDA7535_06 Datasheet
128Kb / 9P
   DELTA/SIGMA CASCADE 20 BIT STEREO DAC
logo
Texas Instruments
TLC320AD75C TI-TLC320AD75C Datasheet
211Kb / 43P
[Old version datasheet]   20-Bit Sigma-Delta Stereo ADA Circuit
logo
STMicroelectronics
TDA7535 STMICROELECTRONICS-TDA7535 Datasheet
160Kb / 9P
   DELTA/SIGMA CASCADE 20 BIT STEREO DAC
logo
Texas Instruments
TLC320AD75 TI1-TLC320AD75 Datasheet
224Kb / 43P
[Old version datasheet]   20-Bit Sigma-Delta Stereo ADA Circuit
logo
STMicroelectronics
TDA7535013TR STMICROELECTRONICS-TDA7535013TR Datasheet
157Kb / 12P
   Delta/sigma cascade 20 bit stereo DAC
logo
Cirrus Logic
CS5510 CIRRUS-CS5510 Datasheet
406Kb / 24P
   16-bit and 20-bit, 8-pin Sigma-Delta ADC
logo
Motorola, Inc
MC145073 MOTOROLA-MC145073 Datasheet
228Kb / 16P
   Dual 16-Bit Stereo Audio Sigma-Delta ADC
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com