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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADC12D1600 Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADC12D1600 Arkusz danych(HTML) 7 Page - Texas Instruments |
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7 / 73 page  GND VA GND VA GND VA 50 k: VA GND GND VA ADC12D1000, ADC12D1600 www.ti.com SNAS480M – MAY 2010 – REVISED MARCH 2013 Table 2. Control and Status Balls (continued) Ball No. Name Equivalent Circuit Description Calibration cycle initiate. The user can command the device to execute a self-calibration cycle by holding this input high a minimum of tCAL_H after having held it low a minimum of tCAL_L. If this input is held high at the time of power-on, the automatic power-on calibration cycle is inhibited until this D6 CAL input is cycled low-then-high. This pin is active in both ECM and Non-ECM. In ECM, this pin is logically OR'd with the CAL Bit (Addr: 0h, Bit 15) in the Control Register. Therefore, both pin and bit must be set low and then either can be set high to execute an on-command calibration. Calibration Running indication. This output is B5 CalRun logic-high while the calibration sequence is executing. This output is logic-low otherwise. Power Down I- and Q-channel. Setting either input to logic-high powers down the respective I- or Q- channel. Setting either input to logic-low brings the respective I- or Q-channel to an operational state U3 PDI after a finite time delay. This pin is active in both V3 PDQ ECM and Non-ECM. In ECM, each Pin is logically OR'd with its respective Bit. Therefore, either this pin or the PDI and PDQ Bit in the Control Register can be used to power-down the I- and Q-channel (Addr: 0h, Bit 11 and Bit 10), respectively. Test Pattern Mode select. With this input at logic- high, the device continuously outputs a fixed, repetitive test pattern at the digital outputs. In the A4 TPM ECM, this input is ignored and the Test Pattern Mode can only be activated through the Control Register by the TPM Bit (Addr: 0h, Bit 12). Non-Demuxed Mode select. Setting this input to logic-high causes the digital output bus to be in the 1:1 Non-Demuxed Mode. Setting this input to A5 NDM logic-low causes the digital output bus to be in the 1:2 Demuxed Mode. This feature is pin-controlled only and remains active during ECM and Non- ECM. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADC12D1000 ADC12D1600 |
Podobny numer części - ADC12D1600 |
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Podobny opis - ADC12D1600 |
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