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ADC083000CIYB Arkusz danych(PDF) 5 Page - Texas Instruments |
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ADC083000CIYB Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 48 page GND VA 200k 8 pF VCMO AC Couple Enable VA AGND VA AGND 100 50k VA AGND VA AGND 50k Control from VCMO VCMO 100 VA AGND VA AGND 100 VBIAS 50k 50k ADC083000 www.ti.com SNAS358N – JUNE 2006 – REVISED JULY 2009 Pin Descriptions and Equivalent Circuits (continued) Pin Functions Pin No. Symbol Equivalent Circuit Description Sampling Clock Input (Input):LVDS The differential clock signal must be a.c. coupled to 10 CLK+ these pins. The input signal is sampled on both the rising and 11 CLK- falling edge of CLK. See Acquiring the Input for a description of acquiring the input and THE SAMPLE CLOCK INPUT for an overview of the clock inputs. Signal Input (Input):Analog The differential full-scale input range is 600 mVP-P 18 VIN+ when the FSR pin is low, or 820 mVP-P when the FSR pin is high. 19 VIN− In the Extended Control Mode, FSR is determined by the Full-Scale Voltage Adjust register (address 3h, bits 15:7). Sample Clock Reset (Input):LVDS A positive differerntial pulse on these pins is used to reset and synchronize the DCLK outs of multiple converters. See 22 DCLK_RST+ MULTIPLE ADC SYNCHRONIZATION for detailed description. 23 DCLK_RST- When bit 14 in the Configuration Register (address 1h) is set to 1b, these differential DCLK_RST pins are selected. See also pin 15 description. Common Mode Voltage (Output):Analog - The voltage output at this pin is required to be the common mode input voltage at VIN+ and VIN− when d.c. 7 VCMO coupling is used. This pin should be grounded when a.c. coupling is used at the analog input. This pin is capable of sourcing or sinking 100 μA and can drive a load up to 80 pF. See THE ANALOG INPUT. Bandgap Output Voltage 31 VBG (Output):Analog - Capable of 100 μA source/sink and can drive a load up to 80 pF. Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC083000 |
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