ADM696/ADM697

REV. 0

–10–

Replacing the Back-Up Battery

When changing the back-up battery with system power on, spu-

rious resets can occur when the battery is removed. This occurs

If spurious resets during battery replacement are acceptable,

then no action is required. If not, then one of the following solu-

tions should be considered:

capacitor is charging up to change the battery. The leakage

current will charge up the external capacitor towards the

the size of external capacitor and the voltage differential be-

tween the capacitor and the charging voltage supply.

The maximum leakage (charging) current is 1

µA over tem-

size should be chosen such that sufficient time is available to

make the battery replacement.

µA/(V

replacement.

Note that the resistor will discharge the battery slightly.

With a 3 V battery, this will draw around 700 nA. This will

be negligible in most cases.

TYPICAL APPLICATIONS

ADM696

Figure 18 shows the ADM696 in a typical power monitoring,

power for the CMOS RAM.

Power Fail RESET

above 1.3 V. This allows for a power-on reset and prevents re-

reset threshold.

Watchdog Timer

The Watchdog Timer Input (WDI) monitors an I/O line from

the

µP system. This line must be toggled once every 1.6 s to

verify correct software execution. Failure to toggle the line indi-

cates that the

µP system is not correctly executing its program

and may be tied up in an endless loop. If this happens, a reset

pulse is generated to initialize the processor.

If the watchdog timer is not needed the WDI input should be

left floating.

Power Fail Detector

The Power Fail Input, PFI, monitors the input power supply via

a resistive divider network R1 and R2. This input is intended as

an early warning power fail input. The voltage on the PFI input

is compared with a precision 1.3 V internal reference. If the in-

put voltage drops below 1.3 V, a power fail output (PFO) signal

is generated. This warns of an impending power failure and may

be used to interrupt the processor so that the system may be

shut down in an orderly fashion. The resistors in the sensing

network are ratioed to give the desired power fail threshold volt-

RESET threshold so that there is sufficient time available to

complete the shutdown procedure before the processor is

RESET and power is lost.

ADM696

R2

R1

PFO

+5V

V

CC

CMOS RAM

POWER

I/O LINE

µP NMI

µP RESET

µP SYSTEM

µP POWER

V

OUT

RESET

WDI

GND

PFI

V

BATT

BATTERY

+

R4

R3

LL

IN

RESET

Figure 18a. ADM696 Typical Application Circuit A

Figure 18b shows a similar application for the ADM696 but in

this case the PFI input monitors the unregulated input to the

7805 voltage regulator. This gives an earlier warning of an im-

pending power failure. It is useful with processors operating at

low speeds or where there are a significant number of house-

keeping tasks to be completed before the power is lost.

ADM696

R2

R1

PFO

INPUT

POWER

V

CC

V

OUT

WDI

GND

PFI

V

BATT

0.1µF

3V

BATTERY

RESET

OSC IN

OSC SEL

LOW LINE

WDO

SYSTEM STATUS

INDICATORS

CMOS

RAM

I/O LINE

NMI

RESET

A0–A15

µP

BATT

ON

NC

V

CC

LL

IN

µP

POWER

RESET

R4

R3

7805

0.1µF

Figure 18b. ADM696 Typical Application Circuit B