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LM2512ASMX Arkusz danych(PDF) 8 Page - Texas Instruments |
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LM2512ASMX Arkusz danych(HTML) 8 Page - Texas Instruments |
8 / 28 page SER DES LM2512A MPL-1 DES MD0 MD1 MC MD2 GND L A T C H / F I F O Three X 256 X 8 Look Up Table D I T H E R P 2 S PLL S P I I / F SPI_CSX SPI_SDA SPI_SCL PCLK MD0 MD1 MC MD2 PD* TM S/D* LM2512A MD0 MD1 MC MD2 R[7:0] G[7:0] B[7:0] VS, HS, DE PCLK LM2512A SNLS269B – AUGUST 2007 – REVISED MAY 2013 www.ti.com FUNCTIONAL DESCRIPTION The LM2512A is a Mobile Pixel Link (MPL) Serializer that serializes a 24-bit RGB plus three control signals (VS, HS, and DE) to two or three MPL MD lines plus the serial clock MC. Two options are provided: 24-bit RGB data dithering to 18 bits, and an optional Look Up Table. The three 256 X 8-bit RAMs may also be used and is controlled via a 3-wire SPI interface. The LM2512A is compatible with certain discrete MPL Deserializers and also Display Drivers with integrated MPL Deserializers (i.e. FPD95320). Figure 6. General LM2512A Block Diagram BUS OVERVIEW The LM2512A is a multi-lane MPL Serializer that supports a 24-bit RGB source interface. The MPL physical layer is purpose-built for an extremely low power and low EMI data transmission while requiring the fewest number of signal lines. No external line components are required, as termination is provided internal to the MPL receiver. A maximum raw throughput of 480 Mbps (3-lane raw) is possible with this chipset. The MPL interface is designed for use with common 50 Ω to 100Ω lines using standard materials and connectors. Lines may be microstrip or stripline construction. Total length of the interconnect is expected to be less than 20cm. Figure 7. Three MD Lane MPL Interface 8 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM2512A |
Podobny numer części - LM2512ASMX |
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Podobny opis - LM2512ASMX |
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