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74HCT138BQ-Q100 Arkusz danych(PDF) 11 Page - NXP Semiconductors

Numer części 74HCT138BQ-Q100
Szczegółowy opis  3-to-8 line decoder/demultiplexer; inverting
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74HC_HCT138_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 16 July 2012
11 of 18
NXP Semiconductors
74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 8.
Load circuitry for measuring switching times
VM
VM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VM
VM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC
VCC
VI
VO
RT
RL
S1
CL
open
G
Table 9.
Test data
Type
Input
Load
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74HC138-Q100
VCC
6ns
15pF, 50 pF
1 k
open
GND
VCC
74HCT138-Q100 3 V
6 ns
15 pF, 50 pF
1 k
open
GND
VCC


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