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AD9516-5BCPZ Arkusz danych(PDF) 9 Page - Analog Devices

Numer części AD9516-5BCPZ
Szczegółowy opis  14-Output Clock Generator
Download  76 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9516-5BCPZ Arkusz danych(HTML) 9 Page - Analog Devices

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AD9516-5
Rev. A | Page 9 of 76
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 8.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL;
uses rising edge of clock signal
CLK = 2.4 GHz; VCO Div = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
210
fs rms
Calculated from SNR of ADC method
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL;
uses rising edge of clock signal
CLK = 2.4 GHz; VCO Div = 2; LVDS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
285
fs rms
Calculated from SNR of ADC method
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL;
uses rising edge of clock signal
CLK = 2.4 GHz; VCO Div = 2; CMOS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
350
fs rms
Calculated from SNR of ADC method
DELAY BLOCK ADDITIVE TIME JITTER
Table 9.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DELAY BLOCK ADDITIVE TIME JITTER1
Incremental additive jitter
100 MHz Output
Delay (1600 μA, 0x1C) Fine Adjust 000000b
0.54
ps rms
Delay (1600 μA, 0x1C) Fine Adjust 101111b
0.60
ps rms
Delay (800 μA, 0x1C) Fine Adjust 000000b
0.65
ps rms
Delay (800 μA, 0x1C) Fine Adjust 101111b
0.85
ps rms
Delay (800 μA, 0x4C) Fine Adjust 000000b
0.79
ps rms
Delay (800 μA, 0x4C) Fine Adjust 101111b
1.2
ps rms
Delay (400 μA, 0x4C) Fine Adjust 000000b
1.2
ps rms
Delay (400 μA, 0x4C) Fine Adjust 101111b
2.0
ps rms
Delay (200 μA, 0x1C) Fine Adjust 000000b
1.3
ps rms
Delay (200 μA, 0x1C) Fine Adjust 101111b
2.5
ps rms
Delay (200 μA, 0x4C) Fine Adjust 000000b
1.9
ps rms
Delay (200 μA, 0x4C) Fine Adjust 101111b
3.8
ps rms
1 This value is incremental; that is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.


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