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ADSP-2184LBST-160 Arkusz danych(PDF) 8 Page - Analog Devices |
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ADSP-2184LBST-160 Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 48 page Rev. C | Page 8 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L RESET The RESET signal initiates a master reset of the ADSP-218xL. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence, the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the mini- mum pulse width specification (tRSP). The RESET input contains some hysteresis; however, if an RC circuit is used to generate the RESET signal, the use of an exter- nal Schmitt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. The first instruction is fetched from on- chip program memory location 0x0000 once boot loading completes. MEMORY ARCHITECTURE The ADSP-218xL series provides a variety of memory and peripheral interface options. The key functional groups are Pro- gram Memory, Data Memory, Byte Memory, and I/O. Refer to Figure 4 through Figure 7 for PM and DM memory allocations in the ADSP-218xL series. Program Memory Program Memory (Full Memory Mode) is a 24-bit-wide space for storing both instruction opcodes and data. The member DSPs of this series have up to 32K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces, using the external data bus. Program Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). External program execution is not available in Host Mode due to a restricted data bus that is only 16 bits wide. Data Memory Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped con- trol registers. The ADSP-218xL series has up to 32K words of Data Memory RAM on-chip. Part of this space is used by 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register. Data Memory (Host Mode) allows access to all internal mem- ory. External overlay access is limited by a single external address line (A0). Figure 3. External Crystal Connections CLKIN CLKOUT XTAL DSP 1M Figure 4. ADSP-2184 Memory Architecture PROGRAM MEMORY PM OVERLAY 1,2 (EXTERNAL PM) INTERNAL PM PM OVERLAY 0 (RESERVED) RESERVED MODEB = 0 0x3FFF 0x2000 0x0000 0x0FFF 0x1000 0x1FFF 0x3FFF 0x2000 0x0000 0x3FE0 0x3FDF 0x3000 0x2FFF 0x1FFF DATA MEMORY DM OVERLAY 1,2 (EXTERNAL DM) INTERNAL DM 32 MEMORY-MAPPED CONTROL REGISTERS 4064 RESERVED WORDS DM OVERLAY 0 (RESERVED) PROGRAM MEMORY RESERVED EXTERNAL PM MODEB = 1 0x3FFF 0x2000 0x0000 0x1FFF |
Podobny numer części - ADSP-2184LBST-160 |
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Podobny opis - ADSP-2184LBST-160 |
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