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AM29LV004T-90RFI Arkusz danych(PDF) 7 Page - Advanced Micro Devices |
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AM29LV004T-90RFI Arkusz danych(HTML) 7 Page - Advanced Micro Devices |
7 / 36 page Am29LV004 7 PR EL I M I NAR Y DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Am29LV004 Device Bus Operations Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out Note: Addresses are A18–A0. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the mem- ory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that as- sert valid addresses on the device address inputs pro- duce valid data on the device data outputs. The device remains enabled for read access until the com- mand register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifica- tions and to Figure 12 for the timing diagram. ICC1 in the DC Characteristics table represents the active cur- rent specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector ad- dress” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteris- tics” for timing diagrams. Operation CE# OE# WE# RESET# Addresses (See Note) DQ0–DQ7 Read L L H H AIN DOUT Write L H L H AIN DIN Standby VCC ± 0.3 V XX VCC ± 0.3 V X High-Z Output Disable L H H H X High-Z Reset X X X L X High-Z Temporary Sector Unprotect X X X VID AIN DIN |
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