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AM53CF96 Arkusz danych(PDF) 1 Page - Advanced Micro Devices |
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AM53CF96 Arkusz danych(HTML) 1 Page - Advanced Micro Devices |
1 / 76 page This document contains information on a product under development at Advanced Micro Devices Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 17348 Rev. B Amendment /0 Issue Date: May 1993 Advanced Micro Devices Am53CF94/Am53CF96 Enhanced SCSI-2 Controller (ESC) PRELIMINARY DISTINCTIVE CHARACTERISTICS s Pin/function compatible with Emulex FAS216/236 s AMD’s Patented programmable GLITCH EATERTM Circuitry on REQ and ACK inputs s 10 Mbytes/s synchronous Fast SCSI transfer rate s 20 Mbytes/s DMA transfer rate s 16-Bit DMA interface plus 2 bits of parity s Flexible three bus architecture s Single-ended SCSI bus supported by Am53CF94 s Differential SCSI bus supported by Am53CF96 s Selection of multiplexed or non-multiplexed address and data bus s High current drivers (48 mA) for direct connection to the single-ended SCSI bus s Supports Disconnect and Reselect commands s Supports burst mode DMA operation with a threshold of eight s Supports 3-byte tagged-queueing as per the SCSI-2 specification s Supports group 2 and 5 command recognition as per the SCSI-2 specification s Advanced CMOS process for lower power consumption s AMD’s exclusive programmable power-down feature s 24-Bit extended transfer counter allows for data block transfer of up to 16 Mbytes s Independently programmable 3-byte message and group 2 identification s Additional check for ID message during bus-initiated Select with ATN s Reselection has QTAG features of ATN3 s Access FIFO Command s Delayed enable signal for differential drivers avoid contention on SCSI differential lines s Programmable Active Negation on REQ, ACK and Data lines s Register programmable control of assertion/ deassertion delay for REQ and ACK lines s Part-unique ID code s Am53CF94 available in 84-pin PLCC package s Am53CF96 available in 100-pin PQFP package s Am53CF94 available in 3.3 V version s Supports clock operating frequencies from 10 MHz–40 MHz s Supports Scatter-Gather or Back-to-Back synchronous data transfers GENERAL DESCRIPTION The Enhanced SCSI-2 Controller (ESC) was designed to support Fast SCSI-2 transfer rates of up to 10 Mbytes/s in synchronous mode and up to 7 Mbytes/s in the asynchronous mode. The ESC is downward com- patible with the Am53C94/96, combining its functionality with features such as Fast SCSI, programmable Active Negation, a 24-bit transfer counter, and a part-unique ID code containing manufacturer and serial # information. AMD’s proprietary features such as power-down mode for SCSI transceivers, programmable GLITCH EATER, and extended Target command set are also included for improved product performance. The Enhanced SCSI-2 Controller (ESC) has a flexible three bus architecture. The ESC has a 16-bit DMA inter- face, an 8-bit host data interface and an 8-bit SCSI data interface. The ESC is designed to minimize host inter- vention by implementing common SCSI sequences in hardware. An on-chip state machine reduces protocol overheads by performing the required sequences in re- sponse to a single command from the host. Selection, reselection, information transfer and disconnection commands are directly supported. The 16-byte-internal FIFO further assists in minimizing host involvement. The FIFO provides a temporary stor- age for all command, data, status and message bytes as they are transferred between the 16-bit host data bus and the 8-bit SCSI data bus. During DMA operations the FIFO acts as a buffer to allow greater latency in the DMA channel. This permits the DMA channel to be sus- pended for higher priority operations such as DRAM re- fresh or reception of an ISDN packet. Parity on the DMA bus is optional. Parity can either be generated and checked or it can be simply passed through. The Target command set for the Am53CF94/96 in- cludes an additional command, the Access FIFO com- mand, to allow the host or DMA controller to remove re- maining FIFO data following the host’s issuance of a Target abort DMA command or following an abort due to |
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