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LF3311 Arkusz danych(PDF) 9 Page - LOGIC Devices Incorporated

Numer części LF3311
Szczegółowy opis  Horizontal / Vertical Digital Image Filter
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Producent  LODEV [LOGIC Devices Incorporated]
Strona internetowa  http://www.logicdevices.com
Logo LODEV - LOGIC Devices Incorporated

LF3311 Arkusz danych(HTML) 9 Page - LOGIC Devices Incorporated

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DEVICES INCORPORATED
LF3311
Horizontal / Vertical Digital Image Filter
Improved Performance
LOGIC Devices Incorporated
9
9/19/05 LDS.3311-C
Video Imaging Products
An output limiting function is provided for the output of the vertical filter. The vertical limit registers determine
the valid range of output values when limiting is enabled (Bit 0 in Configuration Register 5). There are
sixteen 24-bit vertical limit registers. VRSL3-0 determines which vertical limit register is used during the limit
operation. A value of 0 on VRSL3-0 selects vertical limit register 0. A value of 1 selects vertical limit register
1 and so on. Each limit register contains both an upper and lower limit value. If the value fed to the limiting
circuitry is less than the lower limit, the lower limit value is passed as the filter output. If the value fed to the
limiting circuitry is greater than the upper limit, the upper limit value is passed as the filter output. VRSL3-0
may be changed every clock cycle if desired. This allows the limit range to be changed every clock cycle.
This is useful when filtering interleaved data. When loading limit values into the device, the upper limit must
be greater than the lower limit. Limit register loading is discussed in the LF Interface™ section.
Vertical Limiting
Functional Description
BITS
FUNCTION
DESCRIPTION
11-0
Line Buffer Length
See Line Buffer Description Section
Table 4. Configuration Register 2 - Address 202H
BITS
FUNCTION
DESCRIPTION
0
Line Buffer Mode
0 : Delay Mode
1 : Recirculate Mode
1
Line Buffer Load
0 : Normal Load
1 : Parallel Load
11-2
Reserved
Must be set to “0”
Table 5. Configuration Register 3 - Address 203H
Table 3. Configuration Register 1 - Address 201H
BITS
FUNCTION
DESCRIPTION
0
Odd-Tap Interleave Mode
0 : Odd-Tap Interleave Mode Disabled
1 : Odd-Tap Interleave Mode Enabled
4-1
I/D Register Length
0000 : 1 Register
0001 : 2 Registers
0010 : 3 Registers
0011 : 4 Registers
0100 : 5 Registers
0101 : 6 Registers
0110 : 7 Registers
0111 : 8 Registers
1000 : 9 Registers
1001 : 10 Registers
1010 : 11 Registers
1011 : 12 Registers
1100 : 13 Registers
1101 : 14 Registers
1110 : 15 Registers
1111 : 16 Registers
5
Horizontal Tap Number
0 : Even Number of Taps
1 : Odd Number of Taps
6
Horizontal Data Reversal
0 : Data Reversal Enabled
1 : Data Reversal Disabled
11-7
Reserved
Must be set to “0”


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