AD7631

Rev. A | Page 11 of 32

Pin No.

Mnemonic

Type1

Description

37

REF

AO/I

Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled

producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled,

allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF

capacitor is required with or without the internal reference and buffer. See the Voltage Reference

Input/Output section.

38

REFGND

AI

Reference Input Analog Ground. Connected to analog ground plane.

39

IN−

AI

Analog Input. Referenced to IN+.

and centered about 0 V.

In all ranges, IN− must be driven 180° out of phase with IN+.

40

VCC

P

High Voltage Positive Supply. Normally +7 V to +15 V.

41

VEE

P

High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges).

43

IN+

AI

Analog Input. Referenced to IN−.

and centered about 0 V.

In all ranges, IN+ must be driven 180° out of phase with IN−.

45

TEMP

AO

Temperature Sensor Analog Output. When the internal reference is enabled (PDREF = PDBUF = low),

this pin outputs a voltage proportional to the temperature of the AD7631. See the Voltage Reference

Input/Output section.

46

REFBUFIN

AI

Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low,

PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference

Input/Output section.

47

PDREF

DI

Internal Reference Power-Down Input.

When low, the internal reference is enabled.

When high, the internal reference is powered down, and an external reference must be used.

48

PDBUF

DI

Internal Reference Buffer Power-Down Input.

When low, the buffer is enabled (must be low when using internal reference).

When high, the buffer is powered down.

49

EPAD3

NC

Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be soldered

to VEE.

connection.

Hardware Configuration section and the Software Configuraion section.

Table 7. Data Bus Interface Definition

MODE

MODE1

MODE0

D0/OB/2C

D1/A0

D2/A1

D[3]

D[4:9]

D[10:11]

D[12:15]

D[16:17]

Description

0

0

0

R[0]

R[1]

R[2]

R[3]

R[4:9]

R[10:11]

R[12:15]

R[16:17]

18-bit parallel

1

0

1

OB/2C

A0 = 0

R[2]

R[3]

R[4:9]

R[10:11]

R[12:15]

R[16:17]

16-bit high word

1

0

1

OB/2C

A0 = 1

R[0]

R[1]

All zeros

16-bit low word

2

1

0

OB/2C

A0 = 0

A1 = 0

All High-Z

R[10:11]

R[12:15]

R[16:17]

8-bit high byte

2

1

0

OB/2C

A0 = 0

A1 = 1

All High-Z

R[2:3]

R[4:7]

R[8:9]

8-bit midbyte

2

1

0

OB/2C

A0 = 1

A1 = 0

All High-Z

R[0:1]

All zeros

8-bit low byte

2

1

0

OB/2C

A0 = 1

A1 = 1

All High-Z

All zeros

R[0:1]

8-bit low byte

3

1

1

OB/2C

All High-Z

Serial interface

Serial interface