AD7631

Rev. A | Page 9 of 32

Pin No.

Mnemonic

Type1

Description

11, 12

D[4:5] or

DI/O

When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.

DIVSCLK[0:1]

When MODE[1:0] = 3, serial data clock division selection. When using serial master read after convert

mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated

serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs.

13

D6 or

DO/I

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus.

EXT/INT

When MODE[1:0] = 3, Serial Data Clock Source Select. In serial mode, this input is used to select the

internally generated (master) or the external (slave) serial data clock for the AD7631 output data.

When EXT/INT = low (master mode), the internal serial data clock is selected on SDCLK output.

When EXT/INT = high (slave mode), the output data is synchronized to an external clock signal (gated by CS)

connected to the SDCLK input.

14

D7 or

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus.

INVSYNC

When MODE[1:0] = 3, Serial Data Invert Sync Select. In serial master mode (MODE[1:0] = 3,

EXT/INT = low), this input is used to select the active state of the SYNC signal.

When INVSYNC = low, SYNC is active high.

When INVSYNC = high, SYNC is active low.

15

D8 or

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus.

INVSCLK

When MODE[1:0] = 3, Invert SDCLK/SCCLK Select. This input is used to invert both SDCLK and SCCLK.

When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.

When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.

16

D9 or

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 9 of the parallel port data output bus.

RDC or

When MODE[1:0] = 3, Serial Data Read During Convert. In serial master mode (MODE[1:0] = 3,

EXT/INT = low), RDC is used to select the read mode. See the

section.

When RDC = low, the current result is read after conversion. Note the maximum throughput is

not attainable in this mode.

When RDC = high, the previous conversion result is read during the current conversion.

Master Serial Interface

SDIN

When MODE[1:0] = 3, Serial Data In. In serial slave mode (MODE[1:0] = 3, EXT/INT = high), SDIN can

be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single

SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after

the initiation of the read sequence.

18

OVDD

P

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host

interface 2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors.

19

DVDD

P

Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can

be supplied from AVDD.

20

DGND

P

Digital Power Ground. Ground reference point for digital outputs. Should be connected to system

digital ground ideally at the same potential as AGND and OGND.

21

D10 or

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus.

SDOUT

When MODE[1:0] = 3, Serial Data Output. In all serial modes, this pin is used as the serial data output

synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7631 provides

the conversion result, MSB first, from its internal shift register. The data format is determined by

the logic level of OB/2C.

When EXT/INT = low (master mode), SDOUT is valid on both edges of SDCLK.

When EXT/INT = high (slave mode):

When INVSCLK = low, SDOUT is updated on SDCLK rising edge.

When INVSCLK = high, SDOUT is updated on SDCLK falling edge.

22

D11 or

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.

SDCLK

When MODE[1:0] = 3, Serial Data Clock. In all serial modes, this pin is used as the serial data clock

input or output, dependent on the logic state of the EXT/INT pin. The active edge where the data

SDOUT is updated depends on the logic state of the INVSCLK pin.