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74CBTLV3253DS Arkusz danych(PDF) 10 Page - NXP Semiconductors |
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74CBTLV3253DS Arkusz danych(HTML) 10 Page - NXP Semiconductors |
10 / 19 page 74CBTLV3253 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 15 December 2011 10 of 19 NXP Semiconductors 74CBTLV3253 Dual 1-of-4 multiplexer/demultiplexer 11. Waveforms Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 14. The data input (nA or nBn) to output (nBn or nA) propagation delays 001aai367 VM VM VM VM VI input 0 V VOH output VOL tPHL tPLH Table 9. Measurement points Supply voltage Input Output VCC VM VI tr = tf VM VX VY 2.3 V to 2.7 V 0.5VCC VCC 2.0 ns 0.5VCC VOL +0.15V VOH 0.15 V 3.0 V to 3.6 V 0.5VCC VCC 2.0 ns 0.5VCC VOL +0.3 V VOH 0.3 V Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 15. Enable and disable times 001aal212 tPLZ tPHZ switch disabled switch enabled VY VX switch enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH nOE, Sn input VI VCC VM VM VOL VOH GND GND tPZL tPZH VM VM |
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