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TPIC44L01DBRG4 Arkusz danych(PDF) 9 Page - Texas Instruments

Numer części TPIC44L01DBRG4
Szczegółowy opis  4-CHAMMEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
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TPIC44L01, TPIC44L02, TPIC44L03
4CHANNEL SERIAL AND PARALLEL LOW SIDE PREFET DRIVER
SLIS062B NOVEMBER 1996 – REVISED AUGUST 2001
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
serial data operation
The TPIC44L01, TPIC44L02, and TPIC44L03 offer serial input interface to the microcontroller to transfer control
data to the predriver and fault data back to the controller. The serial input interface consists of:
D SCLK – Serial clock
D CS – Chip select
D SDI – Serial data input
D SDO – Serial data output
Serial data is shifted into the least significant bit (LSB) of the SDI shift register on the rising edge of the first SCLK
after CS has transitioned from 1 to 0. Four clock cycles are required to shift the first bit from the LSB to the most
significant bit (MSB) of the shift register. Four clock cycles must occur before CS transitions high for proper
control of the outputs. Less than four clock cycles result in fault data being latched into the output control buffer.
Eight bits of data can be shifted into the device, but the first 4 bits shifted out are always the fault data and the
last 4 bits shifted in are always the output control data. A low-to-high transition on CS latches the contents of
the serial shift register into the output control register. A logic 0 input to SDI turns the corresponding parallel
output off and a logic 1 input turns the output on (see Figure 12).
GATE3 ON
GATE2 ON
GATE1 OFF
GATE0 OFF
12
3
4
Present Output Data
New Data
3-State
FLT3
FLT2
FLT1
FLT0
IN3
3-State
SCLK
CS
SDI
New Data
Output Control
Register Data
SDO
(a) 4-Bit Serial Word Example
Figure 12


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