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74LVC1G97GS Arkusz danych(PDF) 7 Page - NXP Semiconductors |
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74LVC1G97GS Arkusz danych(HTML) 7 Page - NXP Semiconductors |
7 / 20 page 74LVC1G97 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 7 December 2011 7 of 20 NXP Semiconductors 74LVC1G97 Low-power configurable multiple function gate 11. Dynamic characteristics [1] Typical values are measured at nominal VCC and at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (C L VCC 2 f o) = sum of outputs. 12. Waveforms Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max tpd propagation delay A, B, C to Y; see Figure 12 [2] VCC = 1.65 V to 1.95 V 1.0 6.0 14.4 1.0 18.0 ns VCC = 2.3 V to 2.7 V 0.5 3.5 8.3 0.5 10.4 ns VCC = 2.7 V 0.5 4.2 8.5 0.5 10.6 ns VCC = 3.0 V to 3.6 V 0.5 3.8 6.3 0.5 7.9 ns VCC = 4.5 V to 5.5 V 0.5 3.0 5.1 0.5 6.4 ns CPD power dissipation capacitance VCC =3.3 V; VI =GND to VCC [3] -22- - - pF Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig 12. Input A, B and C to output Y propagation delay times Y output A, B, C input Y output GND VI VOH VOH VOL VOL VM VM VM VM VM VM tPLH tPLH tPHL tPHL 001aab593 |
Podobny numer części - 74LVC1G97GS |
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Podobny opis - 74LVC1G97GS |
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