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ADS8361IDBQ Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADS8361IDBQ Arkusz danych(HTML) 7 Page - Texas Instruments |
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7 / 29 page  ADS8361 7 SBAS230E www.ti.com SYMBOL DESCRIPTION MIN MAX UNITS COMMENTS tCONV Conversion Time 1.6 μs When TCKP = 100ns tACQ Acquisition Time 0.4 μs When TCKP = 100ns tCKP Clock Period 100 10,000 ns tCKL Clock LOW 40 ns tCKH Clock HIGH 40 ns tF DOUT Fall Time 25 ns tR DOUT Rise Time 30 ns t1 CONVST HIGH 15 ns t2 Address Setup Time 15 ns Address latched on falling edge of CLK cycle ‘2’. t3 Address Hold Time 15 t4 RD Setup Time 15 ns Before falling edge of CLOCK. t5 RD to CS Hold Time 15 ns After falling edge of CLOCK. t6 CONVST LOW 20 ns t7 RD LOW 20 ns t8 CS Setup Time 15 ns Before falling edge of CLOCK (for RD). t9 CLOCK to Data Valid Delay 30 ns Maximum delay following rising edge of CLOCK. t10 Data Valid After CLOCK(3) 1 ns Time data is valid after second rising edge of CLOCK. t11 CS Setup Time 0 ns Before CONVST TIMING CHARACTERISTICS TIMING CHARACTERISTICS Timing Characteristics over recommended operating free-air temperature range TMIN to TMAX, AVDD = 5V, REFIN = REFOUT internal reference +2.5V, fCLK = 10MHz, fSAMPLE = 500kSPS, and BVDD = 2.7 ÷ 5.5V (unless otherwise noted). NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram above. (3) ‘n – 1’ data will remain valid 1ns after rising edge of next CLOCK cycle. CH A/B CH 0/1 A0 RD CS BUSY Serial Data A 1 CLOCK CONVST 23 4 11 10 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 D15 D14 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D15 D14 D13 D12 Serial Data B D15 D14 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D15 D14 D13 D12 CH 0/1 0 t3 t1 tCONV tACQ tCONV t7 t10 t9 t6 tCKH tCKL 0 t2 t11 t4 t8 t8 t5 |
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