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ADS5500 Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADS5500 Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 32 page www.ti.com RESET TIMING CHARACTERISTICS RESET (Pin 35) t1 . 10 ms t2 . 2 ms t3 . 2 ms SEN Active Power Supply (AVDD, DRVDD) SERIAL PROGRAMMING INTERFACE CHARACTERISTICS ADS5522 SBAS320C – MAY 2004 – REVISED FEBRUARY 2007 TIMING CHARACTERISTICS (continued) Typical values given at T A = 25 C, min and max specified over the full recommeded operating temperature range, AV DD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF, unless otherwise noted PARAMETER DESCRIPTION MIN TYP MAX UNIT Time to valid data after coming out of software 1000 power down Clock Wakeup time cycles Time to valid data after stopping and restarting the 1000 clock Latency Time for a sample to propagate to the ADC outputs 17.5 Clock cycles Typical values given at T A = 25 C, min and max specified over the full recommended operating temperature range, AVDD = DRV DD = 3.3 V, and 3-VPP differential clock, unless otherwise noted PARAMETER DESCRIPTION MIN TYP MAX UNIT Switching Specification t1 Power-on delay Delay from power-on of AVDD and DRVDD to RESET pulse active 10 ms t2 Reset pulse width Pulse width of active RESET signal 2 µs t3 Register write delay Delay from RESET disable to SEN active 2 µs Power-up time Delay from power-up of AVDD and DRVDD to output stable 40 ms Figure 2. Reset Timing Diagram The ADS5522 has a three-wire serial interface. The device latches serial data SDATA on the falling edge of serial clock SCLK when SEN is active. • Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge. • Minimum width of data stream for a valid loading is 16 clocks. • Data is loaded at every 16th SCLK falling edge while SEN is low. • In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. • Data can be loaded in multiples of 16-bit words within a single active SEN pulse. • The first 4-bit nibble is the address of the register while the last 12 bits are the register contents. 7 Submit Documentation Feedback |
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