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ADUC7036CCPZ Arkusz danych(PDF) 10 Page - Analog Devices |
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ADUC7036CCPZ Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 132 page ADuC7036 Rev. C | Page 10 of 132 TIMING SPECIFICATIONS SPI Timing Specifications Table 2. SPI Master Mode Timing—Phase Mode = 1 Parameter Description Min Typ Max Unit tSL SCLK low pulse width1 (SPIDIV + 1) × tHCLK ns tSH SCLK high pulse width1 (SPIDIV + 1) × tHCLK ns tDAV Data output valid after SCLK edge2 (2 × tUCLK) + (2 × tHCLK) ns tDSU Data input setup time before SCLK edge 0 ns tDHD Data input hold time after SCLK edge2 3 × tUCLK ns tDF Data output fall time 3.5 ns tDR Data output rise time 3.5 ns tSR SCLK rise time 3.5 ns tSF SCLK fall time 3.5 ns 1 tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. SCLK (POLARITY = 0) SCLK (POLARITY = 1) MOSI MISO MSB IN BITS[6:1] LSB IN LSB BITS[6:1] MSB tSH tSL tSR tDAV tDF tDR tDSU tDHD tSF Figure 2. SPI Master Mode Timing—Phase Mode = 1 |
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