ADUC7036DCPZ datasheet(11/132 Pages) AD

Numer części	ADUC7036DCPZ

Szczegółowy opis	Integrated Precision Battery Sensor for Automotive

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ADuC7036

Rev. C | Page 11 of 132

Table 3. SPI Master Mode—Phase Mode = 0

Parameter

Description

Min

Typ

Max

Unit

tSL

SCLK low pulse width1

(SPIDIV + 1) × tHCLK

ns

tSH

SCLK high pulse width1

(SPIDIV + 1) × tHCLK

ns

tDAV

Data output valid after SCLK edge2

(2 × tUCLK) + (2 × tHCLK)

ns

tDOSU

Data output setup before SCLK edge

0.5 tSL

ns

tDSU

Data input setup time before SCLK edge

0

ns

tDHD

Data input hold time after SCLK edge2

3 × tUCLK

ns

tDF

Data output fall time

3.5

ns

tDR

Data output rise time

3.5

ns

tSR

SCLK rise time

3.5

ns

tSF

SCLK fall time

3.5

ns

1 tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD.

2 tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

tSH

tSL

tSR

tSF

MISO

MSB IN

BITS[6:1]

LSB IN

tDSU

tDHD

MOSI

LSB

BITS[6:1]

MSB

tDAV

tDF

tDR

tDOSU

Figure 3. SPI Master Mode Timing—Phase Mode = 0

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