Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

ADSP-21062KBZ-160 Arkusz danych(PDF) 10 Page - Analog Devices

Numer części ADSP-21062KBZ-160
Szczegółowy opis  SHARC Processor
Download  64 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

ADSP-21062KBZ-160 Arkusz danych(HTML) 10 Page - Analog Devices

Back Button ADSP-21062KBZ-160 Datasheet HTML 6Page - Analog Devices ADSP-21062KBZ-160 Datasheet HTML 7Page - Analog Devices ADSP-21062KBZ-160 Datasheet HTML 8Page - Analog Devices ADSP-21062KBZ-160 Datasheet HTML 9Page - Analog Devices ADSP-21062KBZ-160 Datasheet HTML 10Page - Analog Devices ADSP-21062KBZ-160 Datasheet HTML 11Page - Analog Devices ADSP-21062KBZ-160 Datasheet HTML 12Page - Analog Devices ADSP-21062KBZ-160 Datasheet HTML 13Page - Analog Devices ADSP-21062KBZ-160 Datasheet HTML 14Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 64 page
background image
Rev. F
|
Page 10 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
PIN FUNCTION DESCRIPTIONS
The ADSP-2106x pin definitions are listed below. Inputs identi-
fied as synchronous (S) must meet timing requirements with
respect to CLKIN (or with respect to TCK for TMS, TDI).
Inputs identified as asynchronous (A) can be asserted asynchro-
nously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except
for ADDR31–0, DATA47–0, FLAG3–0, and inputs that have
internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,
TCLKx, RCLKx, LxDAT3–0, LxCLK, LxACK, TMS, and
TDI)—these pins can be left floating. These pins have a
logic-level hold circuit that prevents the input from floating
internally.
Table 3. Pin Descriptions
Pin
Type
Function
ADDR31–0
I/O/T
External Bus Address. The ADSP-2106x outputs addresses for external memory and peripherals on these
pins. In a multiprocessor system, the bus master outputs addresses for read/write of the internal memory
or IOP registers of other ADSP-2106xs. The ADSP-2106x inputs addresses when a host processor or multi-
processing bus master is reading or writing its internal memory or IOP registers.
DATA47–0
I/O/T
External Bus Data. The ADSP-2106x inputs and outputs data and instructions on these pins. 32-bit single-
precision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of the bus. 40-bit
extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short word data is
transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over bits 23–16. Pull-up
resistors on unused DATA pins are not necessary.
MS3–0
O/T
Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of external
memory. Memory bank size must be defined in the ADSP-2106x’s system control register (SYSCON). The
MS3–0 lines are decoded memory address lines that change at the same time as the other address lines.
When no external memory access is occurring, the MS3–0 lines are inactive; they are active however when
a conditional memory access instruction is executed, whether or not the condition is true. MS0 can be used
with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system the MS3–0
lines are output by the bus master.
RD
I/O/T
Memory Read Strobe. This pin is asserted (low) when the ADSP-2106x reads from external memory devices
or from the internal memory of other ADSP-2106xs. External devices (including other ADSP-2106xs) must
assert RD to read from the ADSP-2106x’s internal memory. In a multiprocessing system, RD is output by the
bus master and is input by all other ADSP-2106xs.
WR
I/O/T
Memory Write Strobe. This pin is asserted (low) when the ADSP-2106x writes to external memory devices
or to the internal memory of other ADSP-2106xs. External devices must assert WR to write to the ADSP-
2106x’s internal memory. In a multiprocessing system, WR is output by the bus master and is input by all
other ADSP-2106xs.
PAGE
O/T
DRAM Page Boundary. The ADSP-2106x asserts this pin to signal that an external DRAM page boundary
has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory control register (WAIT).
DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for Bank
0 accesses. In a multiprocessing system, PAGE is output by the bus master
ADRCLK
O/T
Clock Output Reference. In a multiprocessing system, ADRCLK is output by the bus master.
SW
I/O/T
Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous memory devices
(including other ADSP-2106xs). The ADSP-2106x asserts SW (low) to provide an early indication of an
impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write
instruction). In a multiprocessing system, SW is output by the bus master and is input by all other
ADSP-2106xs to determine if the multiprocessor memory access is a read or write. SW is asserted at the same
time as the address output. A host processor using synchronous writes must assert this pin when writing to
the ADSP-2106x(s).
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)


Podobny numer części - ADSP-21062KBZ-160

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Analog Devices
ADSP-21062KBZ-160 AD-ADSP-21062KBZ-160 Datasheet
817Kb / 64P
   SHARC Processor
Rev. F
ADSP-21062KBZ-160 AD-ADSP-21062KBZ-160 Datasheet
949Kb / 64P
   SHARC Processor
Rev. F
More results

Podobny opis - ADSP-21062KBZ-160

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Analog Devices
ADSP-21262 AD-ADSP-21262 Datasheet
1Mb / 44P
   SHARC Processor
REV. A
ADSP-21362 AD-ADSP-21362 Datasheet
2Mb / 52P
   SHARC Processor
REV. A
ADSP-21060CZ-160 AD-ADSP-21060CZ-160 Datasheet
949Kb / 64P
   SHARC Processor
Rev. F
ADSP-21489BSWZ-4B AD-ADSP-21489BSWZ-4B Datasheet
1Mb / 68P
   SHARC Processor
REV. B
ADSP-21477KCPZ-1A AD-ADSP-21477KCPZ-1A Datasheet
1Mb / 76P
   SHARC Processor
REV. C
ADSP-21062LCSZ-160 AD-ADSP-21062LCSZ-160 Datasheet
811Kb / 64P
   SHARC Processor
Rev. F
ADSP-21060KS-160 AD-ADSP-21060KS-160 Datasheet
817Kb / 64P
   SHARC Processor
Rev. F
ADSP-21469BBCZ-3 AD-ADSP-21469BBCZ-3 Datasheet
2Mb / 72P
   SHARC Processor
REV. 0
ADSP-21364 AD-ADSP-21364 Datasheet
853Kb / 52P
   SHARC Processor
Rev. PrB
ADSP-21375 AD-ADSP-21375 Datasheet
1Mb / 42P
   SHARC Processor
Rev. PrB
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com