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CDC7005RGZ Arkusz danych(PDF) 4 Page - Texas Instruments

Numer części CDC7005RGZ
Szczegółowy opis  3.3-V HIGH PERFORMANCE CLOCK SYNTHSIZER AND JITTER CLEANER
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Strona internetowa  http://www.ti.com
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CDC7005RGZ Arkusz danych(HTML) 4 Page - Texas Instruments

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CDC7005
3.3V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
VCC
D7, E3, E4, E5, E6,
E7, E8, F7, G2, G3,
G4, G5, G6, G7
2, 5, 6, 9, 10, 13,
15, 18, 19, 20,
21, 41, 44, 45, 48
Power
3.3-V supply
VCC and AVCC should have always same supply voltage
VCXO_IN
D1
42
I
VCXO LVPECL input
VCXO_INB
E1
43
I
Complementary VCXO LVPECL input
Y[0:4]
F1, H2, H4, H6, G8
46, 3, 7, 11, 16
O
LVPECL output
Y[0:4]B
G1, H3, H5, H7, F8
47, 4, 8, 12, 17
O
Complementary LVPECL output
NOTE 1: If the internal operational amplifier is not used, these pins can be left open.
SPI control interface
The serial interface of the CDC7005 is a simple SPI-compatible interface for writing to the registers of the device.
It consists of three control lines: CTRL_CLK, CTRL_DATA, and CTRL_LE. There are four 32-bit wide registers,
which can be addressed by the two LSBs of a transferred word (bit 0 and bit 1). Every transmitted word must
have 32 bits, starting with MSB first. Each word can be written separately. It is recommended to program Word
0, Word 1, Word 2 and Word 3 right after power up and NPD becomes HIGH. The transfer is initiated with the
falling edge of CTRL_LE; as long as CTRL_LE is high, no data can be transferred. During CTRL_LE, low data
can be written. The data has to be applied at CTRL_DATA and has to be stable before the rising edge of
CTRL_CLK. The transmission is finished by a rising edge of CTRL_LE. With the rising edge of CTRL_LE, the
new word is asynchronously transferred to the internal register (e.g., N, M, P, ...). Each word has to be separately
transmitted by this procedure. Unused or floating inputs must be tied to proper logic level. It is recommend to
use a 20k
Ω or larger pull−up resistor to VCC.
CTRL_DATA
Bit30
Bit2
Bit1
Bit0
CTRL_CLK
CTRL_LE
tsu1
th2
tsu5
tsu6
t7
t4
t3
Bit31 (MSB)
Figure 1. Timing Diagram SPI Control Interface


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